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[求助] IOpad例化问题

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发表于 2019-9-6 13:30:28 | 显示全部楼层 |阅读模式

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使用CSMC.18工艺,在DC综合前添加IOpad,在顶层对IOpad module进行例化;

这个是工艺库中给出module:module pc18o002 (I, PAD, CS3);其中的CS3应该如何连接?

下面是对CS3的介绍,看不太懂,求大神支招:
CS3 pin in p* cells is a leakage current preventing control pin which prevents the leakage
current. It connects to the ground cell named pv0e_dec. The ground cell pv0e_dec contains logic
to detect power-on sequence. When the IO power supply voltage VD33 has been turned on
whereas the core power supply voltage VDD has not yet, CS3 pin will be high and equals to VD33
so as to prevent large uncertain leakage current. When both VD33 and VDD power are turned on,
then CS3 pin will be low and all the I/O cells will be in normal condition.
In CSMC DUP standard IO, different voltages are supplied to the pre-driver(lower voltage) and
post-driver(higher voltage).
(1) Power up Higher Voltage First
A large bus leakage current may occur due to different power on sequence between core
power and I/O power as power up VD33 first than VDD power. Pv0e_dec cell contains power on
sequence detect signal (namely CS3) to mitigate the leakage current efficiently. CS3 signal is
provided to control I/O cells while detecting power on sequence import in higher voltage power
up first. If any power on sequence problem (VD33 first) is detected, CS3 signal will set output
buffers to high Z state. If there is no power on sequence problem, CS3 signal is set to logic 0 and
it will not affect I/O functions.
CS3 signal should be distributed to all cells for better assembling. As a special ground PAD,
at least one pv0e_dec must be provided in each power domain. pv0e_dec provides VSSPST pad
which should be used to replace the existing pv0e in each power domain. For each power
domain, one pv0e_dec cell is needed to provide CS3 signal for other cells in the same domain.
Note: If chose pv0e_dec cell, the “pcut_dec” IO filler cell will not be chosed, as pcut_dec
filler IO cell make “CS3” directly connect to VSS “logic 0”. If chose pcut_dec IO cell, the pv0e_dec
IO function will gone, power up higher voltage first will not be deceted.




 楼主| 发表于 2019-9-6 14:48:23 | 显示全部楼层
自顶,求解
发表于 2019-9-16 20:12:15 | 显示全部楼层
最好看applicaition 的 图
发表于 2019-9-17 21:50:45 | 显示全部楼层
CS3是一个跟其他厂家的IO类似的POC的一个上电保护的控制信号,如果IO电压先开启,有可能会出现倒灌漏电,CS3会把signal的IO全部接起来之后会接到一个pv0e_dec的IO上面,其实就是有一个地。大概是这样,具体你再研究一下你自己发的那段话,里面作用写的很清楚。
发表于 2019-10-23 20:32:33 | 显示全部楼层
解决了吗?楼主
发表于 2019-10-24 10:55:18 | 显示全部楼层
pv0e_dec provides CS3 signal,   ensure  there is ONE pv0e_dec in each power domain, CS3 will be connected by abut IO pad and IO filler cell.
 楼主| 发表于 2019-10-29 18:26:35 | 显示全部楼层


qingx_j 发表于 2019-10-24 10:55
pv0e_dec provides CS3 signal,   ensure  there is ONE pv0e_dec in each power domain, CS3 will be conn ...


您好,这个段话我是明白,但是不知道具体如何去给这个CS3信号,是在综合之前把这个top上同时把pv0e_dec 这个ground_pad 一并例化了,用于generate CS3
 楼主| 发表于 2019-10-29 18:30:38 | 显示全部楼层


dtww 发表于 2019-9-17 21:50
CS3是一个跟其他厂家的IO类似的POC的一个上电保护的控制信号,如果IO电压先开启,有可能会出现倒灌漏电,CS ...


是的,这段话我是明白的,我后来直接在RTL的top层也把它例化了用于generate CS3 ,dc通过了,但是现在在ICC的时候,总是会报错误,就是
Error: Can't find input port 'CS3' on reference to 'pc18d001' in 'logic_col_chip_io'. (LINK-1)
Warning: Unable to resolve reference 'pc18d001' in 'logic_col_chip_io'. (LINK-5)
Error: Can't find input port 'CS3' on reference to 'pc18d001' in 'logic_col_chip_io'. (LINK-1)
Warning: Unable to resolve reference 'pc18d001' in 'logic_col_chip_io'. (LINK-5)
Error: Can't find input port 'CS3' on reference to 'pc18d001' in 'logic_col_chip_io'. (LINK-1)
Warning: Unable to resolve reference 'pc18d001' in 'logic_col_chip_io'. (LINK-5)
Error: Can't find input port 'CS3' on reference to 'pc18d001' in 'logic_col_chip_io'. (LINK-1)
Warning: Unable to resolve reference 'pc18d001' in 'logic_col_chip_io'. (LINK-5)
Error: Can't find input port 'CS3' on reference to 'pc18d001' in 'logic_col_chip_io'. (LINK-1)
Warning: Unable to resolve reference 'pc18d001' in 'logic_col_chip_io'. (LINK-5)

然而这个输入pad  pc18d001在工艺库里完全就没有这个cs3的port存在,很郁闷

发表于 2019-11-11 15:10:03 | 显示全部楼层
这个库做的不怎么样,以前我们有尝试用,后面就放弃用自己的IO了
 楼主| 发表于 2019-11-12 10:41:44 | 显示全部楼层


dtww 发表于 2019-11-11 15:10
这个库做的不怎么样,以前我们有尝试用,后面就放弃用自己的IO了


请问下,放弃自己的IO是什么意思?我现在换成SMIC的库,就走通了。关键时间都耽误了,真难受

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