SAR-ADC输入的问题

zhangyutong1225

全差分和伪差分（正端接信号，负端接VDD/2）性能差的多吗？

yuechuan

Your common mode will shift a lot for pseudo differential input. This can change your comparator behavior

zhangyutong1225

yuechuan 发表于 2019-7-26 22:45
Your common mode will shift a lot for pseudo differential input. This can change your comparator beh ...

两种情况要是ADC输入共模相同呢？

yuechuan

For pseudo differential input:
V+ connected to Vsignal (Assuming varies from 0 - VDD)
V - connected to VDD/2
Your common mode will be changing from VDD/4 to VDD*3/4.
--------------------------------------------------------------------------------
For fully differential input
V+ connected to  Vcom +Vsignal
V- connected to Vcom - Vsignal
Your common mode voltage will always be Vcom
------------------------------------------------------------
They will not have the same common mode voltage if you vary the input.

yuechuan

They cannot be the same.

V+ (0 to VDD)
V- (VDD/2)
V_common (VDD/4 to VDD*3/4)

nanke

对于商用芯片，应该有改变共模的input  buffer,这样只要信号源和PCB做好，性能应该不受影响。

zhangyutong1225

yuechuan 发表于 2019-7-26 23:06
They cannot be the same.

V+ (0 to VDD)

直接相连确实是您说的这样，但是ADC前面有个buffer，buffer的两个输出共模是固定/一样的。

zhangyutong1225

nanke 发表于 2019-7-27 10:40
对于商用芯片，应该有改变共模的input  buffer,这样只要信号源和PCB做好，性能应该不受影响。
...

谢谢，再请教一下buffer前面的滤波器是不是对ADC的SNR影响很大。