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发表于 2020-8-20 03:44:40
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Wha information are you looking for?
Like tool performance?, or what does it do?.
VC Formal is a Formal verification tool that uses SystemVerilog assertions (that defines the properties/behavior of the design) as a "tesbench", and run mathematical models such as Bounded Model Checking (BMC), K-induction, and hybrid engines, to check the entire design state space with the goal of proving that the properties hold. If they do not, a counter example (CEX) is created. A CEX is a short waveform that shows where the design fails, and only uses the relevant signals.
VC Formal uses verdi as front end. VC is not the only formal tool out there. JasperGold from Cadence, OneSpin, and SymbiYosys does the same thing.
If you don't have VC Formal license, you can try SymbiYosys. That tool is free for Verilog 2005. For SystemVerilog you need a license (to use Verific as a parser), but you can request a demo licnse to try that as well.
Let me know if you have further questions. |
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