马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
本帖最后由 lxing_1988 于 2019-6-22 22:54 编辑
The Introduction to the UVM (UniversalVerification Methodology) course consists of twelve sessions that will guideyou from rudimentary SystemVerilog through a complete UVM testbench. Eachsession is designed to give you the minimal amount of knowledge necessary tomake it to the next level. Once you have worked through all these sessions, youwill have experience with all the major components of the UVM as well as theirconcepts. You are then ready to learn more advanced techniques.
| 
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2019-6-22 22:07:26
