在没有改变版图的情况下直接做lvs，为什么还是过不了？

巴甫洛夫很忙 · 发表于 2019-6-13 17:12:58

如题，PT timing clean之后，从ICC写出gds文件和lvs.v文件，然后将lvs.v转为sourc.spi，将gds文件导入到calibre中去，然后跳过DRC检查，直接做lvs检查，理论上来说，我的版图没有动过，source和layout是从同一个cel中写出来的，是同一数据的不同表现形式而已，lvs应该一定过的，为什么还是过不了？

注:label什么的都打了，目前报错好像是incorrect nets

巴甫洛夫很忙 · 发表于 2019-6-13 17:18:00

附上lvs的报告及相关截图

巴甫洛夫很忙 · 发表于 2019-6-13 17:22:52

port和instance的数量都是一致的，但是net数量不一致

巴甫洛夫很忙 · 发表于 2019-6-13 17:31:12

o Statistics:

4 passthrough source nets were deleted.

331 layout instances were filtered and their pins removed from adjoining nets.

102699 layout mos transistors were reduced to 34960.  10851 connecting nets were deleted.
   48380 mos transistors were deleted by parallel reduction.
   19359 mos transistors and 10851 connecting nets were deleted by split-gate reduction.
37991 source mos transistors were reduced to 11981.  10851 connecting nets were deleted.
   6651 mos transistors were deleted by parallel reduction.
   19359 mos transistors and 10851 connecting nets were deleted by split-gate reduction.

4 parallel layout diodes were reduced to 1.
4 parallel source diodes were reduced to 1.

1 layout net had all its pins removed and was deleted.
8121 source nets had all their pins removed and were deleted.

46 nets were matched arbitrarily.

这些数据是什么意思？数据中显示被删掉的net，instance以及46条模糊匹配的net是会对lvs的结果有影响吗？如果有影响的话，应该如何设置以消除这些影响？

liuada001 · 发表于 2019-6-13 18:13:33

你加tap cell了嘛？看起来是因为每家tap cell导致的

巴甫洛夫很忙 · 发表于 2019-6-13 19:01:39

liuada001 发表于 2019-6-13 18:13
你加tap cell了嘛？看起来是因为每家tap cell导致的

smic0.13工艺，好像并不需要加tap cell

liuada001 · 发表于 2019-6-18 16:54:34

巴甫洛夫很忙发表于 2019-6-13 19:01
smic0.13工艺，好像并不需要加tap cell

这个跟工艺没关系，要看你的库有没有自带tap，tapcell是必须要加的，有可能集成到cell内部。你的这个情况，看起来是cell内部本来应该接VDD的接了一根非VDD的线，cell里面除了电源之外，就只有衬底和NW有这种需求了。

学习的小白 · 发表于 2019-6-27 11:51:56

vdd error 感觉也是一些 basic cell没加的问题。.13工艺还真不懂

小马哥爱逛 · 发表于 2019-7-10 10:55:37

是需要加电源和地的label吧，提示的是版图中的线应该连到原理图的VDD

xxd2000li · 发表于 2019-7-11 17:29:15

就是你那条线本来网表接vdd的， layout没接，

[求助] 在没有改变版图的情况下直接做lvs，为什么还是过不了？

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