QRC提取的av_extracted在virtuoso中后仿问题

inuyasha6058

求助各位大神:

最近在做后仿真, 版图参数提取后产生的av_extracted文件挂至pre_layout的schematic底下.

然而仿真的时候报如下错误 (virtuoso ADE explorer):
Error found by spectre during hierarchy flattening.
    ERROR (SFE-46): "input.scs" 3745324: `I4': An instance of `xxx' can have at most 6 terminals (but has 78).

仿真网表input.scs对应行的内容为:
I4 (vdd! 0 address\<7\> address\<6\> address\<5\> address\<4\> \
        address\<3\> address\<2\> address\<1\> address\<0\> clk cs \
        read_data\<31\> read_data\<30\> read_data\<29\> read_data\<28\> \
        read_data\<27\> read_data\<26\> read_data\<25\> read_data\<24\> \
        read_data\<23\> read_data\<22\> read_data\<21\> read_data\<20\> \
        read_data\<19\> read_data\<18\> read_data\<17\> read_data\<16\> \
   .....

按照错误来看, 似乎只识别了单bit端口,bus端口没有识别出来. 下面为pre-layout的综合网表端口定义:
module aes ( clk, reset_n, cs, we, address, write_data, read_data , VDD, VSS);
  input [7:0] address;
  input [31:0] write_data;
  output [31:0] read_data;
  input clk, reset_n, cs, we;
  input VDD,VSS;

...

苦苦搜寻找不到原因, 不知道各位大神知道怎么解决这个问题?

木木木森

请问解决了吗，我也遇到这个问题