请帮我看一看下面的并转串程序，编译不过

7867 · 发表于 2003-9-2 09:51:41

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entity cuanb is
Port ( d_in  : in std_logic_vector(7 downto 0);
         clk  : in std_logic;
         over  : inout std_logic;
         d_out : out std_logic);
end cuanb;
architecture Behavioral of cuanb is
signal  count : integer ;
signal reg : std_logic_vector ( 7  downto 0 );
signal beg : std_logic;
begin
process
begin
wait until  clk ='1' and clk'event ;
if over = '1' then --
reg <= d_in ;
over <= '0';
end if ;
end  process;
process
begin
wait until clk'event and clk ='1' ;
count <= 7 ;
if over = '0' then
ss : while ( count >= 0 ) loop
wait clk = '1' and clk'event ;
d_out <= reg ( 7 - count) ;
count <= count -1;

end loop ss ;
end if ;
over <= '1';
end process;
end Behavioral;