一个8位处理器结构，源码分析

wanghua131

A minimal 8Bit CPU in a 32 Macrocell CLPD.
Tim B¨oscke, t.boescke@tuhh.de
February 17, 2002
This documents describes a successful attempt to fit a simple VHDL - CPU into a 32 macrocell CPLD.
The CPU has been simulated and has so far been synthesized for the Lattice M4A 32/32 (ispDesignExpert
Starter) and the Xilinx 9536 (WebPack). However, all macrocell counts in this document refer to
the M4A 32/32.
The CPU entity description (basically an interface to asynchronous sram):
entity CPU8BIT2 is
port (
data: inout std_logic_vector(7 downto 0);
adress: out std_logic_vector(5 downto 0);
oe: out std_logic;
we: out std_logic;
rst: in std_logic;
clk: in std_logic);
end;

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