请教，关于分频时钟A non-unate path in clock network for clock

cfh123

版主以及各位前辈好，我的设计里包含分频时钟，所以我在DC中这样来约束：

create_generated_clock  -name clk  -source [get_ports RF_CLK] -divide_by 128  [get_pins inst_dec_top/inst_clk_div/clk_reg/Q]

create_generated_clock  -name mclk  -source [get_ports RF_CLK] -divide_by 4   [get_pins inst_dec_top/inst_clk_div/mclk_reg/Q]


然后在综合时报出下述warning：
Warning: A non-unate path in clock network for clock 'clk'
from pin 'inst_dec_top/inst_clk_div/U6/Y' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'mclk'
from pin 'inst_dec_top/inst_clk_div/U3/Y' is detected. (TIM-052)
......

我的源代码是
always @(posedge rf_clk or negedge rst_n)
  if(!rst_n)         clk <= 1'b0;
  else if(counter==6'd63) begin
    if(cur_state==SOF)  clk <= 1'b0;
    else           clk <= ~clk;
  end
  
always @(posedge rf_clk or negedge rst_n)
  if(!rst_n)  mclk <= 1'b0;     
  else if(counter[1:0]==2'b10)   
                  mclk <= ~mclk;

counter是一个6位计数器

请问，我这样约束是否合理呢？然后分频器的RTL代码这样写是否合理呢？我该如何修改才是正确的呢？谢谢大家了，急......file:///C:/Users/CFH/AppData/Local/Temp/ksohtml/wps5104.tmp.png

cfh123

我有试过这样修改
always @(posedge rf_clk or negedge dec_rst_n)
  if(!dec_rst_n)  counter <= 6'd0;
  else            counter <= counter + 1'b1;

assign clk = counter[5];
assign mclk = counter[1];

然后这样约束：
create_generated_clock  -name clk  -source [get_ports RF_CLK] -divide_by 128 [get_pins inst_dec_top/inst_clk_div/counter_reg[5]/Q]
但还是有上述警告。

但像这样约束后，警告才消失：
create_generated_clock  -name clk  -source [get_ports RF_CLK] -divide_by 128 [get_pins inst_dec_top/inst_clk_div/clk]
但这种约束是否合理呢？大家都是怎么做的呀

cfh123

版主勿删。。。因为再后端社区没有人回答我，所以才到前端社区发一贴的，真的急求好的回答。。。

jake

Please try the following.  Please replace ??? with actual values.

create_clock -name CLK_RF -period ??? -waveform {??? ???} [get_port RF_CLK]
create_generated_clock -name CLK_RF_DIV128_GC -master_clock [get_clocks CLK_RF] -source [get_pins inst_dec_top/inst_clk_div/clk_reg/CLK] -divide_by 128  [get_pins inst_dec_top/inst_clk_div/clk_reg/Q]

Note: -source is the CLK pin of the flop whose Q pin is the root of the generated clock.  Instead of -divided_by 128, it might be better to use the -edges {1 129 257}

七点班车

TIM-052
TIM-052 (warning) A non-unate path in clock network for clock '%s' from pin '%s' is detected.
DESCRIPTION
The clock tree for the specified clock contains non-unate paths, which means that the sense
of the signal reaching the clock pin of a sequential device could be either the same or
inverted with respect to the original clock source. This could be caused by the presence of
an XOR gate in the clock path, for example. By default, timing analysis considers the worst
possible arrival times of both positive and negative unate clock edges.
WHAT NEXT
If you do not want both the inverted and non-inverted clock waveforms to reach the clock pin
of a sequential device, use the set_clock_sense command to explicitly specify the sense of
the signal reaching the clock pin, either positive or negative unate, with respect to the clock
source.

cfh123

jake 发表于 2019-4-3 21:44
Please try the following.  Please replace ??? with actual values.

create_clock -name CLK_RF -perio ...

你好，非常感谢你的回答，但是现在有一个问题是我的Q端可以定位到，但寄存器的CLK端无法定位到，提示：
Warning: Can't find object 'inst_dec_top/inst_clk_div/clk_reg/CLK' in design 'baseband'. (UID-95)
请问这个该怎样解决呢？谢谢您！

cfh123

jake 发表于 2019-4-3 21:44
Please try the following.  Please replace ??? with actual values.

create_clock -name CLK_RF -perio ...

您好，谢谢您的回答，只是现在有一个问题是寄存器的CLK端无法定位到，Q端可以定位到，提示：
Warning: Can't find object 'inst_dec_top/inst_clk_div/clk_reg/CLK' in design 'baseband'. (UID-95)
请问这个问题该如何解决呢？非常感谢！

fangwang85

不知道楼主解决了没有？遇到了同样的问题，时钟路径有XOR

geff

cfh123 发表于 2019-4-3 10:09
我有试过这样修改
always @(posedge rf_clk or negedge dec_rst_n)
  if(!dec_rst_n)  counter  ...

个人理解
RTL约束是不是应该定义在Module的port上，而不是REG/Q上。
会不会是没找到该PIN。

cody_wang

七点班车 发表于 2019-4-4 10:02
TIM-052
TIM-052 (warning) A non-unate path in clock network for clock '%s' from pin '%s' is detected ...

I used set_clock_sense -clock -negetive like that , The warning still occurs.