pcie 1.0 and 2.0 vhost-master 代码

zhanweisu33

如题

# pcievhost
PCIe (1.0a to 2.0) Virtual host model for verilog.

Generates PCIe Physical, Data Link and Transaction Layer traffic for up to 16 lanes, controlled from user C program, via an API. Has configurable internal memory and configuration space models, and will auto-generate completions (configurably), with flow control, ACKs, and NAKS etc.

Is bundled with verilog pcie link traffic display modules, and an example test harness. Tested for ModelSim only at the present time, though easily adpated for VCS, NC-Verilog and Icarus (and has previously been running on these in the past).

gyong22

good to study. thanks

ayamitek

thankyou

smrecnik

thanks for sharing

tankysose

感谢分享

musmttt

感谢分享

jlqsczw_2007

good staff

posix6973

take a look, thanks.

gaeazzz

thank you

jimcmwang

PCIe (1.0a to 2.0) Virtual host model for verilog.

Generates PCIe Physical, Data Link and Transaction Layer traffic for up to 16 lanes, controlled from user C program, via an API. Has configurable internal memory and configuration space models, and will auto-generate completions (configurably), with flow control, ACKs, and NAKS etc.

Is bundled with verilog pcie link traffic display modules, and an example test harness. Tested for ModelSim only at the present time, though easily adpated for VCS, NC-Verilog and Icarus (and has previously been running on these in the past).