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发表于 2019-3-23 10:30:19
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显示全部楼层
哈哈 我的是最新版的 lic可以破
xrun: 18.09-s010: (c) Copyright 1995-2019 Cadence Design Systems, Inc.
file: dut_dummy.v
module worklib.dut_dummy:v
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy (primary partition):
xmelab: *N,MEVCON: In multi-run MSIE mode, explicit connectivity access from command-line would be required for tran gate pins, if '$dumpports' is used in the design.
Top level design units:
dut_dummy
xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.dut_dummy:v <0x0ca9ca81>
streams: 17, words: 9380
Building instance specific data structures.
Loading native compiled code: .................... Done
Design hierarchy summary:
Instances Unique
Modules: 1 1
Registers: 6 6
Scalar wires: 71 -
Always blocks: 3 3
Writing primary snapshot: worklib.dut_dummy:v
xrun: 18.09-s010: (c) Copyright 1995-2019 Cadence Design Systems, Inc.
Compiling UVM packages (uvm_pkg.sv cdns_uvm_pkg.sv) using uvmhome location /tools/cadence/XCELIUM1809/tools/methodology/UVM/CDNS-1.1d
file: ubus_tb_top.sv
package worklib.ubus_pkg:sv
errors: 0, warnings: 0
interface worklib.ubus_if:sv
errors: 0, warnings: 0
module worklib.ubus_tb_top:sv
errors: 0, warnings: 0
Loading primary snapshot worklib.dut_dummy:v .................... Done
Caching library 'worklib' ....... Done
Elaborating the design hierarchy (incremental partition):
xmelab: *N,MEVCON: In multi-run MSIE mode, explicit connectivity access from command-line would be required for tran gate pins, if '$dumpports' is used in the design.
[MSIE] Instance ubus_tb_top.dut is bound to module worklib.dut_dummy:v in primary snapshot worklib.dut_dummy:v
Top level design units (incremental partition):
uvm_pkg
cdns_uvmapi
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