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自己想编写一个卷积模块,用HLS的fft函数来实现,一共需要3个fft函数。C simulation和C synthesis都通过,但到C/RTL Co-simulation遇到问题,提示如下:
ERROR: [VRFC 10-1374] size mismatch in mixed language port association, vhdl port s_axis_data_tdata [F:/FPGA_Exam/hls/conv/conv_prj/solution1/sim/verilog/fft_config1_s.v:47]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
ERROR: Please check the snapshot name which is created during 'xelab',the current snapshot name "xsim.dir/conv_top/xsimk.exe" does not exist
哪位有空帮我分析分析,哪里的原因,找了好几天了。非常感谢!
模块文件如下:
- #include "conv_top.h"
- void dummy_proc_fe(
- cmpxDataIn in[IFFT_LENGTH],
- cmpxDataIn out[IFFT_LENGTH])
- {
- int i;
- for (i=0; i< IFFT_LENGTH; i++)
- out[i] = in[i];
- }
- void array_multipl(
- complex<data_in_t> in_one[IFFT_LENGTH],
- complex<data_in_t> in_two[IFFT_LENGTH],
- complex<data_out_t> out_multipl[IFFT_LENGTH])
- {
- int i;
- array_multipl_label0:for(i=0; i<IFFT_LENGTH; i++)
- {
- out_multipl[i] = in_one[i] * in_two[i];
- }
- }
- void conv_top(
- complex<data_in_t> in1[IFFT_LENGTH],
- complex<data_in_t> in2[IFFT_LENGTH],
- complex<data_out_t> out_conv[IFFT_LENGTH])
- {
- complex<data_in_t> xn[IFFT_LENGTH]; //ifft
- status_t ifft_status;
- config_t ifft_config;
- complex<data_in_t> xn1[IFFT_LENGTH]; //single_one fft
- complex<data_out_t> xk1[IFFT_LENGTH];
- status_t fft_status1;
- config_t fft_config1;
- complex<data_in_t> xn2[IFFT_LENGTH]; //single_two fft
- complex<data_out_t> xk2[IFFT_LENGTH];
- status_t fft_status2;
- config_t fft_config2;
- dummy_proc_fe(in1, xn1);
- dummy_proc_fe(in2, xn2);
- fft_config1.setDir(1);
- fft_config2.setDir(1);
- ifft_config.setDir(0);
- hls::fft<config1>(xn1, xk1, &fft_status1, &fft_config1);
- hls::fft<config1>(xn2, xk2, &fft_status2, &fft_config2);
- array_multipl(xk1,xk2,xn);
- hls::fft<config1>(xn, out_conv, &ifft_status, &ifft_config);
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头文件如下:
- #include "ap_fixed.h"
- #include "hls_fft.h"
- // configurable params
- const char FFT_INPUT_WIDTH = 32;
- const char FFT_OUTPUT_WIDTH = FFT_INPUT_WIDTH;
- const char FFT_STATUS_WIDTH = 8;
- const char FFT_CONFIG_WIDTH = 16;
- const char FFT_NFFT_MAX = 10;
- const char IFFT_NFFT_MAX = 11;
- const int FFT_LENGTH = 1 << FFT_NFFT_MAX;
- const int IFFT_LENGTH = 1 << IFFT_NFFT_MAX;
- typedef float data_in_t; //定义为浮点数
- typedef float data_out_t; //定义为浮点数
- #include <complex>
- typedef std::complex<data_in_t> cmpxDataIn;
- typedef std::complex<data_out_t> cmpxDataOut;
- using namespace std;
- struct config1 : hls::ip_fft::params_t { //静态参数,fft函数用到
- static const unsigned ordering_opt = hls::ip_fft::natural_order;
- static const unsigned config_width = FFT_CONFIG_WIDTH;
- static const unsigned status_width = FFT_STATUS_WIDTH;
- static const unsigned phase_factor_width = 24;
- static const unsigned scaling_opt = hls::ip_fft::unscaled; //不适用缩放因子
- static const unsigned max_nfft = 11; //
- static const unsigned mem_phase_factors = hls::ip_fft::distributed_ram;
- static const unsigned stages_block_ram = 3;
- };
- typedef hls::ip_fft::config_t<config1> config_t; //fft运行时间的配置
- typedef hls::ip_fft::status_t<config1> status_t; //fft运行时间的状态
- void dummy_proc_fe(
- cmpxDataIn in[IFFT_LENGTH],
- cmpxDataOut out[IFFT_LENGTH]);
- void array_multipl(
- complex<data_in_t> in_one[IFFT_LENGTH],
- complex<data_in_t> in_two[IFFT_LENGTH],
- complex<data_out_t> out_multipl[IFFT_LENGTH]);
- void conv_top(
- complex<data_in_t> in1[IFFT_LENGTH],
- complex<data_in_t> in2[IFFT_LENGTH],
- complex<data_out_t> out_conv[IFFT_LENGTH]);
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directives.tcl如下:
- ############################################################
- ## This file is generated automatically by Vivado HLS.
- ## Please DO NOT edit it.
- ## Copyright (C) 2015 Xilinx Inc. All rights reserved.
- ############################################################
- set_directive_dataflow "conv_top"
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