急！请斑竹帮我看看！

fanxg88

我用xilinx的foundation来开发xc9500的cpld，在运行流程中，TRANSLATE成功通过，在FIT时，窗口显示
ngdbuild -p xc95108-10-pc84 -uc cnt16.ucf -dd .. c:\xilinx\active\projects\cnt16\cnt16.edn cnt16.ngd
Release 4.1i - ngdbuild E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Command Line: ngdbuild -p xc95108-10-pc84 -uc cnt16.ucf -dd ..
c:\xilinx\active\projects\cnt16\cnt16.edn cnt16.ngd
Launcher: Executing edif2ngd "c:\xilinx\active\projects\cnt16\cnt16.edn"
"c:\xilinx\active\projects\cnt16\xproj\ver1\cnt16.ngo"
INFO:NgdBuild - Release 4.1i - edif2ngd E.30
INFO:NgdBuild - Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Writing the design to "c:/xilinx/active/projects/cnt16/xproj/ver1/cnt16.ngo"...
Reading NGO file "c:/xilinx/active/projects/cnt16/xproj/ver1/cnt16.ngo" ...
Reading component libraries for design expansion...
Launcher: Executing edif2ngd -noa
"c:\xilinx\active\projects\cnt16\R_SY_D_FF.edf"
"c:\xilinx\active\projects\cnt16\xproj\ver1\R_SY_D_FF.ngo"
INFO:NgdBuild - Release 4.1i - edif2ngd E.30
INFO:NgdBuild - Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/xilinx/active/projects/cnt16/xproj/ver1/R_SY_D_FF.ngo"...
Loading design module
"c:\xilinx\active\projects\cnt16\xproj\ver1\R_SY_D_FF.ngo"...
Launcher: Executing edif2ngd -noa "c:\xilinx\active\projects\cnt16\R_TFF.edf"
"c:\xilinx\active\projects\cnt16\xproj\ver1\R_TFF.ngo"
INFO:NgdBuild - Release 4.1i - edif2ngd E.30
INFO:NgdBuild - Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Writing the design to "c:/xilinx/active/projects/cnt16/xproj/ver1/R_TFF.ngo"...
Loading design module "c:\xilinx\active\projects\cnt16\xproj\ver1\R_TFF.ngo"...
Launcher: Executing edif2ngd -noa
"c:\xilinx\active\projects\cnt16\BUF_SEL_2.edf"
"c:\xilinx\active\projects\cnt16\xproj\ver1\BUF_SEL_2.ngo"
INFO:NgdBuild - Release 4.1i - edif2ngd E.30
INFO:NgdBuild - Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/xilinx/active/projects/cnt16/xproj/ver1/BUF_SEL_2.ngo"...
Loading design module
"c:\xilinx\active\projects\cnt16\xproj\ver1\BUF_SEL_2.ngo"...
Annotating constraints to design from file "cnt16.ucf" ...
Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'U7/U4/BO' has no load
WARNING:NgdBuild:454 - logical net 'U7/U4/CO' has no load
NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   2
Writing NGD file "cnt16.ngd" ...
Writing NGDBUILD log file "cnt16.bld"...
NGDBUILD done.
==================================================
hitop -f cnt16.ngd -d cnt16 -s -l cnt16.log -o cnt16
Release 4.1i - Optimizer/Partitioner E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Considering device XC95108-PC84.
Flattening design..
Multi-level logic optimization...
Timing optimization............................................................
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 64 equations into 6 function blocks.........
Design cnt16 has been optimized and fit into device XC95108-10-PC84.
==================================================
taengine -f cnt16 -l cnt16.tim
Release 4.1i - Timing Report Generator E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Path tracing .....
ABORTING
==================================================
hitop -f cnt16.ngd -d cnt16 -s -l cnt16.log -o cnt16
Release 4.1i - Optimizer/Partitioner E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Considering device XC95108-PC84.
Flattening design..
Multi-level logic optimization...
Timing optimization............................................................
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 64 equations into 6 function blocks.........
Design cnt16 has been optimized and fit into device XC95108-10-PC84.
==================================================
taengine -f cnt16 -l cnt16.tim
Release 4.1i - Timing Report Generator E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Path tracing .....
就一直保持不动，而且系统也不报错！

fanxg88

附件是运行图！

atuhappy

没用过

jackzhang

试着用ISE试试
如果设计不复杂，最好能公开你的设计，让大家替你跑一下

fanxg88

我有ISEWEPACK设计软件，但没有ISE，不知道哪里可以下载或者买到！

zhoujj

到xilinx官方网站去下

CliffZhang

是啊，fundation太老了，换新的看看