Design for Reliability of Low-voltage Switched-capacitor Circuits 下载

xinhunlei

再传点开关电容电路的资料，这资料可与模拟大师Gray有关系的哦


Design for Reliability of Low-voltage,
Switched-capacitor Circuits
by
Andrew Masami Abo
Doctor of Philosophy in Engineering
University of California, Berkeley
Professor Paul R. Gray, Chair
Analog, switched-capacitor circuits play a critical role in mixed-signal, analogto-
digital interfaces. They implement a large class of functions, such as sampling,
filtering, and digitization. Furthermore, their implementation makes them
suitable for integration with complex, digital-signal-processing blocks in a compatible,
low-cost technology–particularly CMOS. Even as an increasingly larger
amount of signal processing is done in the digital domain, this critical, analogto-
digital interface is fundamentally necessary. Examples of some integrated applications
include camcorders, wireless LAN transceivers, digital set-top boxes,
and others.
Advances in CMOS technology, however, are driving the operating voltage of
integrated circuits increasingly lower. As device dimensions shrink, the applied
voltages will need to be proportionately scaled in order to guarantee long-term
reliability and manage power density.
The reliability constraints of the technology dictate that the analog circuitry
operate at the same low voltage as the digital circuitry. Furthermore, in achieving
low-voltage operation, the reliability constraints of the technology must not be
violated.
This work examines the voltage limitations of CMOS technology and how analog
circuits can maximize the utility of MOS devices without degrading relia-
1
bility. An emphasis is placed on providing circuit solutions that do not require
process enhancements. The specific research contributions of this work include
(1) identifying the MOS device reliability issues that are relevant to switchedcapacitor
circuits, (2) introduction of a new bootstrap technique for operating
MOS transmission gates on a low voltage supply without significantly degrading
device lifetime, (3) development of low-voltage opamp design techniques. With
these design techniques building blocks necessary for switched-capacitor circuits
can be implemented, enabling the creation of sampling, filtering, and data conversion
circuits on low-voltage supplies. As a demonstration, the design and characterization
of an experimental 1.5V, 10-bit, 14.3MS/s, CMOS pipeline analogto-
digital converter is presented.
Paul R. Gray, Chair

Chapter 1 Introduction 1
Chapter 2 Switched-Capacitor Building Blocks 5
2.1 Sample-and-hold (S/H) . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Top-plate S/H. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 Bottom-plate S/H . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Gain stage . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Integrator . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4 Comparator . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 3 Switched-Capacitor Applications 19
3.1 Filters . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Sigma-delta analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3 Pipeline Analog-to-digital converters .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4 Capacitor digital-to-analog converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 4 CMOS Technology Scaling 33
4.1 CMOS Scaling . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2 Voltage scaling for low power .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3 Voltage scaling for reliability .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3.1 Gate oxide breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3.2 Hot-electron effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.4 Fundamental scaling limits .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
iii
iv CONTENTS
4.5 Analog circuit integration . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Chapter 5 Low-voltage Circuit Design 49
5.1 Low-voltage, switched-capacitor design issues . . . . . . . . . . . . . . . . . . . . . 49
5.2 Reliable, high-swingMOS switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2.1 Operation . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2.2 Design guidelines . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.2.3 Layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3 Opamp . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.1 Application . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3.2 Topology.. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3.3 Biasing. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3.4 Linear Settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.5 Slew rate. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3.6 Noise. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3.7 DC gain . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.3.8 Common-mode feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.4 Comparator . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.4.1 Offset . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.4.2 Meta-stability. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.4.3 Pre-amplifier bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Chapter 6 Pipeline ADC Architecture 85
6.1 Pipeline ADC architecture... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.2 1.5-bit/stage architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3 1.5 bit/stage implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.4 Pipeline stage accuracy requirements .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.1 Capacitor matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.2 Capacitor linearity .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.4.3 Opamp DC gain . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.4.4 Opamp settling . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.4.5 Thermal noise . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
CONTENTS v
6.4.6 Error tolerances . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.4.7 Design example . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Chapter 7 Prototype Implementation 99
7.1 Technology . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2 Layout . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.3 Master bias . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
7.4 Clock generator . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
7.5 Capacitor trimming . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
7.6 Gain stage . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
7.7 Sub-ADC/DAC . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Chapter 8 Experimental Results 111
8.1 Test setup . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.2 Dynamic linearity and noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.3 Static linearity. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8.4 Summary . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Chapter 9 Conclusion 119
Bibliography 121
Index 128

semico_ljj

很一般的资料！

zowal

这篇文章在pipeline AD设计中有很大的影响力度

LAS.xs

kankan

jeffcfwong

正須要用呢, 謝謝!

woai008

看一下！！呵呵

mao_junhua1

thanks

keroppi

看起來是不錯的入門文件
從原理 到LAYOUT都要提到
小弟先在此謝過了

peter_hawks

thanks a lot