LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY switch IS
PORT
(turn_on: INbit;
turn_off: IN bit;
state : OUT bit);
END switch;
ARCHITECTURE struct OF switch IS
BEGIN
PROCESS (turn_on)
BEGIN
IF (turn_on'EVENT AND turn_on = '0') THEN
IF turn_off='1' THEN
state<='1';
END IF;
END IF;
END PROCESS;
PROCESS (turn_off)
BEGIN
IF (turn_off'EVENT AND turn_off = '0') THEN
IF turn_on='1' THEN
state<='0';
END IF;
END IF;
END PROCESS;
END STRUCT;
出错信息:
unresolved sigal is mutiply driven.
请大家指点。
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY switch IS
PORT(
turn_on: IN bit;
turn_off: IN bit;
state : OUT bit);
END switch;
ARCHITECTURE struct1 OF switch IS
TYPE STATE_TYPE IS (s0, s1);
SIGNAL X: STATE_TYPE;
BEGIN
PROCESS (turn_on)
BEGIN
IF (turn_on'EVENT AND turn_on = '0') THEN
IF turn_off='1' THEN
X <= S0;
else
X <= S1;
END IF;
END IF;
END PROCESS;
STATE <= '1' WHEN X = s0
ELSE '0';
END STRUCT1;
ARCHITECTURE struct2 OF switch IS
TYPE STATE_TYPE IS (s0, s1);
SIGNAL Y: STATE_TYPE;
BEGIN
PROCESS (TURN_OFF)
BEGIN
IF (turn_OFF'EVENT AND turn_OFF = '0') THEN
IF turn_oN='1' THEN
Y <= S1;
else
Y <= S0;
END IF;
END IF;
END PROCESS;
STATE <= '1' WHEN Y = s0
ELSE '0';
END STRUCT2;
修改了一下,没有仿真不知道对不对。呵呵