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向大家推荐一个非常好的描述如何从系统设计角度分析和确定各种模拟部件设计参数的文章。希望大家不但知道如何被人告知参数后如何设计单个器件本身,还能了解从系统角度如何折中分析和设计各个器件的参数和对系统最终性能的影响(反应到系统的BER/BLER等)。如何对种种器件进行数学建模和仿真,加入到系统建模和仿真中来。而不仅仅是一个最初始的snr budget分析。
List of Figures vii
List of Tables xiii
Acknowledgments xv
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Research Goals 2
1.3 Thesis Organization 3
Chapter 2 Receiver Architectures 5
2.1 Introduction 5
2.2 Heterodyne Architecture 7
2.2.1 The Image Problem 7
2.2.2 Implementation 8
2.3 Direct-Conversion Architecture 9
2.3.1 DC Offsets 10
2.3.2 Flicker Noise 12
2.4 Image-Reject Architecture 13
2.4.1 Practical Considerations 16
2.5 Low-IF Architecture 17
2.5.1 Digital Frequency Translation to Baseband 17
2.6 Receiver Architecture Selection 19
2.6.1 Direct-Conversion Architecture 20
2.6.2 Image-Reject Architecture 21
2.6.3 Low-IF Architecture 22
2.6.4 Receiver Architecture Selection Guidelines 23
Chapter 3 Receiver Impairments 25
3.1 Introduction 25
3.2 Quadrature Phase-Shift Keying Modulation 26
3.3 Receiver Noise 27
3.4 Gain Mismatch 30
3.5 Quadrature Phase Mismatch 32
3.6 Frequency Offset 35
3.7 LO Phase Noise 37
3.8 Receiver Distortion 39
3.9 Filtering 40
3.10 DC Offsets 45
Table of Contents
iv
3.11 ADC Quantization 46
3.12 Summary 48
Chapter 4 System-Level Simulation Framework 49
4.1 Introduction 49
4.2 Receiver Performance Calculations 49
4.2.1 Noise Calculations 50
4.2.2 Distortion Calculations 53
4.2.3 Summary 58
4.3 Baseband-Equivalent Models 59
4.3.1 RF Amplifiers 60
4.3.2 Local Oscillators 60
4.3.3 Mixers 61
4.3.4 Summary 64
4.4 Simulation Framework Implementation 64
4.4.1 Thermal Noise 65
4.4.2 Flicker Noise 67
4.4.3 RF Amplifiers 70
4.4.4 Mixers 71
4.4.5 Local Oscillators 72
4.4.6 Baseband Amplifiers and Filters 75
4.4.7 Analog-to-Digital Converters 76
4.4.8 Receiver Performance Metrics 80
4.5 Summary 80
Chapter 5 A High-Speed Wireless Downlink 83
5.1 Introduction 83
5.2 Base-Station Transmitter 83
5.2.1 Multiple Access Method and Power Control 84
5.2.2 Pulse Shaping 85
5.2.3 Pilot Channel/Symbol 87
5.2.4 Mobility Support: Picocells 87
5.2.5 Analog Front-End 88
5.3 Mobile Receiver 90
5.3.1 Propagation Models 90
5.3.2 Receiver Sensitivity 92
5.3.3 Receiver Processing Gain 94
5.3.4 Receiver Architecture 96
5.3.5 Flicker-Noise Suppression 96
5.3.6 DC-Offset Compensation 98
5.3.7 Receiver Noise Figure 103
5.3.8 ADC Performance 103
5.3.9 Receiver Gain 108
5.3.10 Receiver Distortion 109
5.3.11 Receiver AGC Loop 109
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5.3.12 Multiuser Detection 121
5.3.13 Summary 127
5.4 System Simulation 129
5.4.1 Base-Station Transmitter 129
5.4.2 Channel Model 130
5.4.3 Mobile Receiver 131
5.4.4 Simulation Outputs 131
5.5 Summary 133
Chapter 6 Receiver Prototype 135
6.1 Introduction 135
6.2 Low-Noise Amplifier 136
6.2.1 Microwave Filter Design 137
6.2.2 LNA Performance Metrics 140
6.2.3 Transistor Noise Model 141
6.2.4 Matching for Minimum Noise Figure 147
6.2.5 LNA Topologies 151
6.2.6 Inductively-Degenerated Differential LNA 167
6.3 Frequency Synthesizer 178
6.3.1 Voltage-Controlled Oscillator 180
6.3.2 Other Design Considerations 182
6.4 Mixer 183
6.4.1 Passive Mixers 183
6.4.2 Active Mixers 185
6.4.3 Mixer Implementation 185
6.5 Baseband Amplification and Filtering 187
6.5.1 Low-Pass Filtering 187
6.6 Implementation of Baseband Amplifiers and Filters 192
6.7 Analog-to-Digital Converter 197
6.7.1 Pipeline Architecture 197
6.7.2 Timing Recovery Considerations 198
6.7.3 Sigma-Delta Analog-to-Digital Converter 200
6.8 Receiver Test Chips 200
Chapter 7 Simulated Performance and Measurement Results 205
7.1 Simulated Performance 205
7.1.1 LNA/Mixer/Baseband Simulations 205
7.1.2 LNA/Mixer/PLL/Baseband Simulation 207
7.1.3 LNA/Mixer/PLL/Baseband/ADC Simulation 208
7.2 Measurement Results 209
7.3 Measurement Issues 216
7.3.1 Yield and Reliability 217
7.3.2 Packaging Technology 217
Chapter 8 Conclusion 219
vi
8.1 Research Summary 219
8.2 Future Work 220
8.2.1 Bottom-Up Verification 221
8.2.2 Improved Behavioral Models 221
8.2.3 Single-Chip Integration 222
Appendix A Baseband-Equivalent Models 225
A.1 RF Amplifiers 225
A.2 Mixers 227
Appendix B DC-Offset Cancellation 231
B.1 Introduction 231
B.2 Alternative DC-Offset Cancellation Techniques 231
Appendix C Why 50 Ω? 237
C.1 Introduction 237
C.2 Impedance Matching for Maximum Power Transfer 238
C.3 Impedance Matching for Minimum Noise Figure 241
C.4 Impedance Matching for Maximum Voltage Transfer 242
C.4.1 Common-Source LNA 245
C.4.2 Inductively-Degenerated Common-Source LNA 247
C.5 Antenna Circuit Model 249
C.6 Summary 251
Appendix D Inductor Test Structures 253
D.1 Introduction 253
D.2 ASITIC Simulation Results 255
D.3 Test Chip Layout 255
D.4 Measurement Results 256
References 259 |
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