求救modelsim 后仿真（。VQM）出错

风过尘扬

vsim -L D:/EDA/modelsim/Modeltech_6.1f/Altera_lib/cycloneii/cycloneii -Lf D:/EDA/modelsim/Modeltech_6.1f/Altera_lib/altera_librarys -hazards -multisource_delay min -sdftyp /count_10_test=D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10_v.sdo -t ps work.count_10_test
# vsim -L D:/EDA/modelsim/Modeltech_6.1f/Altera_lib/cycloneii/cycloneii -Lf D:/EDA/modelsim/Modeltech_6.1f/Altera_lib/altera_librarys -hazards -multisource_delay min -sdftyp /count_10_test=D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10_v.sdo -t ps work.count_10_test
# Loading work.count_10_test
# Loading work.count_10
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(80): Unresolved reference to 'q_c0' in q_c0.lut_mask.
#         Region: /count_10_test/cnt
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(81): Unresolved reference to 'q_c0' in q_c0.sum_lutc_input.
#         Region: /count_10_test/cnt
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(92): Unresolved reference to 'q_c1' in q_c1.lut_mask.
#         Region: /count_10_test/cnt
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(93): Unresolved reference to 'q_c1' in q_c1.sum_lutc_input.
#         Region: /count_10_test/cnt
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(104): Unresolved reference to 'q_c2' in q_c2.lut_mask.
#         Region: /count_10_test/cnt
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(105): Unresolved reference to 'q_c2' in q_c2.sum_lutc_input.
#         Region: /count_10_test/cnt
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(115): Unresolved reference to 'q_c3' in q_c3.lut_mask.
#         Region: /count_10_test/cnt
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(116): Unresolved reference to 'q_c3' in q_c3.sum_lutc_input.
#         Region: /count_10_test/cnt
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(130): Unresolved reference to 'reset_in' in reset_in.operation_mode.
#         Region: /count_10_test/cnt
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(144): Unresolved reference to 'clk_in' in clk_in.operation_mode.
#         Region: /count_10_test/cnt
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(157): Unresolved reference to 'q_out_3_' in q_out_3_.operation_mode.
#         Region: /count_10_test/cnt
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(170): Unresolved reference to 'q_out_2_' in q_out_2_.operation_mode.
#         Region: /count_10_test/cnt
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(183): Unresolved reference to 'q_out_1_' in q_out_1_.operation_mode.
#         Region: /count_10_test/cnt
# ** Error: (vsim-3043) D:/EDA/modelsim/Modeltech_6.1f/examples/verilog/count_10_test/count_10.vqm(196): Unresolved reference to 'q_out_0_' in q_out_0_.operation_mode.
#         Region: /count_10_test/cnt
# Error loading design

风过尘扬

我这几天学习用modelsim se 6.1f, 用的QUARTUS2 5.1SP2，以上是我在modelsim下仿真网表文件（。VQM）出的错，库应该都建好了，我实在是没有办法了，我都郁闷了好几天了，希望各位大哥给我分析分析，小弟万分感谢，下面是我编的测试程序和源程序
`timescale 1ns/1ns
module count_10_test;
reg    reset,clk;
reg[3:0] q;
parameter tp=340;

initial
begin
     reset=1;
     #20 reset=0;
     #tp reset=1;
end

always #10 clk=~clk;
count_10 cnt(.q(q),.clk(clk),.reset(reset));

endmodule
源程序如下：
module count_10(clk,q,reset);
input  clk,reset;
output[3:0] q;
reg[3:0]    q;

always @(posedge clk)
begin
     if(!reset)
        q<=q+1;
     else
       q<=4'b0;
end

endmodule

风过尘扬

下面是网表文件：大家帮我看看，谢谢了
module count_10 (
  clk,
  q,
  reset
);
input clk ;
output [3:0] q ;
input reset ;
wire clk ;
wire reset ;
wire [3:0] qz;
wire VCC ;
wire GND ;
wire q_c0_combout ;
wire clk_c ;
wire reset_c ;
wire q_c1_combout ;
wire q_c2_combout ;
wire q_c3_combout ;
wire q_c0_cout ;
wire q_c1_cout ;
wire q_c2_cout ;
//@1:1
  assign VCC = 1'b1;
//@1:1
  assign GND = 1'b0;
// @5:7
  cycloneii_lcell_ff q_0__Z (
        .regout(qz[0]),
        .datain(q_c0_combout),
        .clk(clk_c),
        .sclr(reset_c)
);
// @5:7
  cycloneii_lcell_ff q_1__Z (
        .regout(qz[1]),
        .datain(q_c1_combout),
        .clk(clk_c),
        .sclr(reset_c)
);
// @5:7
  cycloneii_lcell_ff q_2__Z (
        .regout(qz[2]),
        .datain(q_c2_combout),
        .clk(clk_c),
        .sclr(reset_c)
);
// @5:7
  cycloneii_lcell_ff q_3__Z (
        .regout(qz[3]),
        .datain(q_c3_combout),
        .clk(clk_c),
        .sclr(reset_c)
);
// @5:7
  cycloneii_lcell_comb q_c0 (
        .combout(q_c0_combout),
        .cout(q_c0_cout),
        .dataa(qz[0]),
        .datab(VCC),
        .datac(VCC),
        .datad(VCC)
);
defparam q_c0.lut_mask="6688";
defparam q_c0.sum_lutc_input="cin";
// @5:7
  cycloneii_lcell_comb q_c1 (
        .combout(q_c1_combout),
        .cout(q_c1_cout),
        .dataa(qz[1]),
        .datab(VCC),
        .datac(VCC),
        .datad(VCC),
        .cin(q_c0_cout)
);
defparam q_c1.lut_mask="5aa0";
defparam q_c1.sum_lutc_input="cin";
// @5:7
  cycloneii_lcell_comb q_c2 (
        .combout(q_c2_combout),
        .cout(q_c2_cout),
        .dataa(qz[2]),
        .datab(VCC),
        .datac(VCC),
        .datad(VCC),
        .cin(q_c1_cout)
);
defparam q_c2.lut_mask="5aa0";
defparam q_c2.sum_lutc_input="cin";
// @5:7
  cycloneii_lcell_comb q_c3 (
        .combout(q_c3_combout),
        .dataa(qz[3]),
        .datab(VCC),
        .datac(VCC),
        .datad(VCC),
        .cin(q_c2_cout)
);
defparam q_c3.lut_mask="5a5a";
defparam q_c3.sum_lutc_input="cin";
// @5:3
  cycloneii_io reset_in (
        .padio(reset),
        .combout(reset_c),
        .datain(GND),
        .oe(GND),
        .outclk(GND),
        .outclkena(VCC),
        .inclk(GND),
        .inclkena(VCC),
        .areset(GND),
        .sreset(GND)
);
defparam reset_in.operation_mode = "input";
// @5:3
  cycloneii_io clk_in (
        .padio(clk),
        .combout(clk_c),
        .datain(GND),
        .oe(GND),
        .outclk(GND),
        .outclkena(VCC),
        .inclk(GND),
        .inclkena(VCC),
        .areset(GND),
        .sreset(GND)
);
defparam clk_in.operation_mode = "input";
// @5:5
  cycloneii_io q_out_3_ (
        .padio(q[3]),
        .datain(qz[3]),
        .oe(VCC),
        .outclk(GND),
        .outclkena(VCC),
        .inclk(GND),
        .inclkena(VCC),
        .areset(GND),
        .sreset(GND)
);
defparam q_out_3_.operation_mode = "output";
// @5:5
  cycloneii_io q_out_2_ (
        .padio(q[2]),
        .datain(qz[2]),
        .oe(VCC),
        .outclk(GND),
        .outclkena(VCC),
        .inclk(GND),
        .inclkena(VCC),
        .areset(GND),
        .sreset(GND)
);
defparam q_out_2_.operation_mode = "output";
// @5:5
  cycloneii_io q_out_1_ (
        .padio(q[1]),
        .datain(qz[1]),
        .oe(VCC),
        .outclk(GND),
        .outclkena(VCC),
        .inclk(GND),
        .inclkena(VCC),
        .areset(GND),
        .sreset(GND)
);
defparam q_out_1_.operation_mode = "output";
// @5:5
  cycloneii_io q_out_0_ (
        .padio(q[0]),
        .datain(qz[0]),
        .oe(VCC),
        .outclk(GND),
        .outclkena(VCC),
        .inclk(GND),
        .inclkena(VCC),
        .areset(GND),
        .sreset(GND)
);
defparam q_out_0_.operation_mode = "output";
endmodule /* count_10 */

风过尘扬

郁闷死了，换了版本就可以。哎