一篇分频好文章:Clock Dividers Made Easy

BABABA

文章开头的摘要:

Dividing a clock by an even number always generates 50% duty cycle output. Sometimes it is
necessary to generate a 50% duty cycle frequency even when the input clock is divided by an
odd or non-integer number. This paper talks about implementation of unusual clock dividers.
The paper starts up with simple dividers where the clock is divided by an odd number (Divide by
3, 5 etc) and then later expands it into non-integer dividers (Divide by 1.5, 2.5 etc). The circuits
are simple, efficient and are cheaper and faster than any external PLL alternatives. This paper
also covers Verilog code implementation for a non-integer divider.

xurunze

看看楼主的东东

Avalon

看看先，谢谢，楼主了

vhdlboy

不错!

ccsky218

先看一下

Bomber123

thank you~~

lxandlj

下来看看,

zjun726

最近正在研究时钟分频，lz的东西真是及时啊。