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Session 5 – Oversampling A/D Converters
Cedar Ballroom, Monday Morning, September 17
Chair: Jennifer Lloyd
Co-Chair: Un-Ku Moon
This session highlights recent advances in oversampling ADCs including dynamic range improvements for both bandpass and lowpass modulators and improved tolerance for analog imperfections.
10:00 am
Introduction
5.1 - 10:05 am
A 63-mA 112/94-dB DR IF Bandpass Delta-Sigma Modulator with Direct Feed-forward and Double Sampling
T. Yamamoto, M. Kasahara and T. Matsuura, Renesas Technology Corp.
5.2 - 10:30 am
A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR
K. Yamamoto, A. Chan Carusone and F. Dawson, University of Toronto
5.3 - 10:55 am
A 94dB SFDR 78dB DR 2.2MHz BW Multi-bit Delta-Sigma Modulator with Noise Shaping DAC
J. Chen and Y.P. Xu, National University of Singapore
5.4 - 11:20 am
A 18mW CT ΔΣ Modulator with 25MHz Bandwidth for Next Generation Wireless Applications
X. Chen, Y. Wang, G. Temes, Oregon State University, Y. Fujimoto, P. Lo Ré, Y. Kanazawa, Sharp Corp., J. Steensgaard, Esion LLC
5.5 - 11:45 am
Multi-Bit Sigma Delta ADC with Reduced Feedback Levels, Extended Dynamic Range and Increased Tolerance for Analog Imperfections
J.-Y. Wu, R. Subramoniam, Z. Zhang, A. Djabbari, P. Holloway
M. Yousefi, M. Aslan, H. Hong and A. Bahai, National Semiconductor, F. Maloberti, University of Pavia |
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