2007 CICC section 13 Clocking and CDRs

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The Conference. list the papers:

Session 13 – Clocking and CDRs

Fir Ballroom, Tuesday Morning, September 18

Chair :  Jafar Savoj

Co-Chair:  Kimo Tam

This session explores modern clocking techniques with an emphasis on digital enhancement along with new CDR implementations.

8:25 am

Introduction

13.1  -  8:30 am

Low-Jitter and Large-EMI-Reduction Spread-Spectrum Clock Generator with Auto-Calibration for Serial-ATA Application

T. Kawamoto, Hitachi Ltd., T. Takahashi, H. Inada and T. Noto, Renesas Technology

13.2  -  8:55 am

Wide Lock-Range, Low Phase-Noise PLL using Interpolative Ring-VCO with Coarse Frequency Tuning and Frequency Linearization

H. Kodama, H. Okada, H. Ishikawa and A. Tanaka, NEC Corporation

13.3  -  9:20 am

A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance

M. Brownlee, P. Hanumolu and U.-K. Moon, Oregon State University

13.4  -  9:45 am

A 2.5Gb/s Burst-Mode CDR based on a 1/8th Rate Dual Pulse Ring Oscillator

S. Gierkink, Conexant

10:10 am - BREAK

13.5  -  10:25 am

Digitally-Enhanced Phase-Locking Circuits (INVITED PAPER)

P. Hanumolu, U.-K. Moon and K. Mayaram, Oregon State University, G.-Y. Wei, Harvard University

13.6  -  11:15 am

A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time

M.-Y. Kim, D. Shin, H. Chae, S. Ok and C. Kim, Korea University

13.7  -  11:40 am

An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface

J.-H. Bae, J.-Y. Sim, H.-J. Park, POSTECH and J.-H. Seo, H.-S. Yeo, J.-W. Kim,Samsung Electronics

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