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最近在学mips，共享mips资料

see mips run

Contents
Foreword i
Preface xv
0.1 Style and Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
0.2 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii
0.3 Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii
1 RICSs and MIPS 1
1.1 Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.1 What Makes a Pipeline Inefficient? . . . . . . . . . . . . . 3
1.1.2 The Pipeline and Caching . . . . . . . . . . . . . . . . . . . 4
1.2 The MIPS Five-Stage Pipeline . . . . . . . . . . . . . . . . . . . . . 5
1.3 RISC and CISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Great MIPS Chips of the Past and
Present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4.1 R2000 to R3000 . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4.2 R6000: A Diversion . . . . . . . . . . . . . . . . . . . . . . 8
1.4.3 The R4000 Revolution . . . . . . . . . . . . . . . . . . . . . 9
1.4.4 R5000 and R10000 . . . . . . . . . . . . . . . . . . . . . . 9
1.5 MIPS Compared with CISC Architectures . . . . . . . . . . . . . 12
1.5.1 Constraints on Instructions . . . . . . . . . . . . . . . . . 12
1.5.2 Addressing and Memory Accesses . . . . . . . . . . . . . . 13
1.5.3 Features You Won’t Find . . . . . . . . . . . . . . . . . . . 14
1.5.4 A Feature You Might Not Expect . . . . . . . . . . . . . . . 16
1.5.5 Programmer-Visible Pipeline Effects . . . . . . . . . . . . . 16
2 MIPS Architecture 19
2.1 A Flavor of MIPS Assembly Language . . . . . . . . . . . . . . . . 20
2.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.1 Conventional Names and Uses of General-
Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . 23
2.3 Integer Multiply Unit and Registers . . . . . . . . . . . . . . . . . 25
2.4 Loading and Storing: Addressing Modes . . . . . . . . . . . . . . 27
2.5 Data Types in Memory and Registers . . . . . . . . . . . . . . . . 27
2.5.1 Integer Data Types . . . . . . . . . . . . . . . . . . . . . . . 28
2.5.2 Unaligned Loads and Stores . . . . . . . . . . . . . . . . . 28
2.5.3 Floating-Foint Data in Memory . . . . . . . . . . . . . . . . 29
2.6 Synthesized Instructions in Assembly
Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.7 MIPS I to MIPS IV 64-Bit (and Other) Extensions . . . . . . . . . 32
2.7.1 To 64 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.7.2 Who Needs 64 Bits? . . . . . . . . . . . . . . . . . . . . . . 33
2.7.3 Regarding 64 Bits and No Mode Switch: Data in Registers 34
2.7.4 Other Innovations in MIPS III . . . . . . . . . . . . . . . . 35
2.8 Basic Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.8.1 Addressing in Simple Systems . . . . . . . . . . . . . . . . 39
2.8.2 Kernel vs. User Privilege Level . . . . . . . . . . . . . . . . 40
2.8.3 The Full Picture: The 64-Bit view of the Memory Map . . 40
2.9 Pipeline Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3 Coprocessor 0: MIPS Processor Control 45
3.1 CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . 48
3.2 What Registers Are Relevant When? . . . . . . . . . . . . . . . . . 49
3.3 Encodings of Standard CPU Control
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.1 Processor ID (PRId) Register . . . . . . . . . . . . . . . . . 51
3.3.2 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . 52
3.3.3 Cause Register . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.4 Exception Return Address (EPC) Register . . . . . . . . . 58
3.3.5 Bad Virtual Address (BadVaddr) Register . . . . . . . . . . 58
3.4 Control Registers for the R4000 CPU and Followers . . . . . . . 59
3.4.1 Count/Compare Registers: The R4000 Timer . . . . . . . 60
3.4.2 Config Register: R4x00 Configuration . . . . . . . . . . . . 60
3.4.3 Load-Linked Address (LLAddr) Register . . . . . . . . . . . 63
3.4.4 Debugger Watchpoint (WatchLo/
WatchHi) Registers . . . . . . . . . . . . . . . . . . . . . . . 63
4 Caches for MIPS 65
4.1 Caches and Cache Management . . . . . . . . . . . . . . . . . . . 65
4.2 How Caches Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.3 Write-Through Caches in Early MIPS CPUs . . . . . . . . . . . . 69
4.4 Write-Back Caches in Recent MIPS CPUs . . . . . . . . . . . . . 69
4.5 Other Choices in Cache Design . . . . . . . . . . . . . . . . . . . 71
4.6 Managing Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.7 Secondary and Tertiary Caches . . . . . . . . . . . . . . . . . . . 77
4.8 Cache Configuration for MIPS CPUs . . . . . . . . . . . . . . . . 77
4.9 Programming R3000-Style Caches . . . . . . . . . . . . . . . . . 77
4.9.1 Using Cache Isolation and Swapping . . . . . . . . . . . . 79
4.9.2 Initializing and Sizing . . . . . . . . . . . . . . . . . . . . . 80
4.9.3 Invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.9.4 Testing and Probing . . . . . . . . . . . . . . . . . . . . . . 82
4.10Programming R4000-Style Caches . . . . . . . . . . . . . . . . . 82
4.10.1CacheERR, ERR, and ErrorEPC Registers:
Cache Error Handling . . . . . . . . . . . . . . . . . . . . . 84
4.10.2The Cache Instruction . . . . . . . . . . . . . . . . . . . . . 85
4.10.3Cache Sizing and Figuring Out Configuration . . . . . . . 85
4.10.4Initialization Routines . . . . . . . . . . . . . . . . . . . . . 85
4.10.5Invalidating or Writing Back a Region of Memory in the
Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.11Cache Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.12Reorganizing Software to Influence Cache Efficiency . . . . . . . 93
4.13Write Buffers and When You Need to Worry . . . . . . . . . . . . 95
4.13.1Implementing wbfiush . . . . . . . . . . . . . . . . . . . . . 97
4.14More about MIPS Caches . . . . . . . . . . . . . . . . . . . . . . . 98
4.14.1Multiprocessor Cache Features . . . . . . . . . . . . . . . 98
4.14.2Cache Aliases . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Exceptions, Interrupts, and Initialization 101
5.1 Precise Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.2 When Exceptions Happen . . . . . . . . . . . . . . . . . . . . . . 104
5.3 Exception Vectors: Where Exception Handling Starts . . . . . . 105
5.4 Exception Handling: Basics . . . . . . . . . . . . . . . . . . . . . 109
5.5 Returning from an Exception . . . . . . . . . . . . . . . . . . . . . 110
5.6 Nesting Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.7 An Exception Routine . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.8.1 Interrupt Resources in MIPS CPUs . . . . . . . . . . . . . 112
5.8.2 Implementing Interrupt Priority . . . . . . . . . . . . . . . 114
5.8.3 Atomicity and Atomic Changes to SR . . . . . . . . . . . . 116
5.8.4 Critical Regions with Interrupts Enabled: Semaphores
the MIPS Way . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.9 Starting Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.9.1 Probing and Recognizing Your CPU . . . . . . . . . . . . . 121
5.9.2 Bootstrap Sequences . . . . . . . . . . . . . . . . . . . . . 122
5.9.3 Starting Up an Application . . . . . . . . . . . . . . . . . . 123
5.10Emulating Instructions . . . . . . . . . . . . . . . . . . . . . . . . 124
Memory Management and the TLB 125
6.1 Memory Management in Big Computers . . . . . . . . . . . . . . 127
6.1.1 Basic Process Layout and Protection . . . . . . . . . . . . 127
6.1.2 Mapping Process Addresses to Real Memory . . . . . . . . 129
6.1.3 Paged Mapping Preferred . . . . . . . . . . . . . . . . . . . 130
6.1.4 What We Really Want . . . . . . . . . . . . . . . . . . . . . 131
6.1.5 Origins of the MIPS Design . . . . . . . . . . . . . . . . . . 133
6.2 MIPS TLB Facts and Figures . . . . . . . . . . . . . . . . . . . . . 133
6.3 MMU Registers Described . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.1 EntryHi, EntryLo, and PageMask . . . . . . . . . . . . . . 136
6.3.2 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.3 Random . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.4 Wired . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.5 Context and XContext . . . . . . . . . . . . . . . . . . . 141
6.4 MMU Control Instructions . . . . . . . . . . . . . . . . . . . . . . 142
6.5 Programming the TLB . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.5.1 How Refill Happens . . . . . . . . . . . . . . . . . . . . . . 144
6.5.2 Using ASIDs . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.5.3 The Random Register and Wired Entries . . . . . . . . . . 145
6.6 Memory Translation: Setup . . . . . . . . . . . . . . . . . . . . . 146
6.7 TLB Exception Sample Code . . . . . . . . . . . . . . . . . . . . . 147
6.7.1 The 32-Bit R3000-Style User TLB Miss Exception Handler 148
6.7.2 TLB Miss Exception Handler for R4x00 CPU . . . . . . . . 151
6.7.3 XTLB Miss Handler . . . . . . . . . . . . . . . . . . . . . . 154
6.8 Keeping Track of Modified Pages (Simulating “Dirty” Bits) . . . . 154
6.9 Memory Translation and 64-Bit Pointers . . . . . . . . . . . . . . 155
6.10Everyday Use of the MIPS TLB . . . . . . . . . . . . . . . . . . . . 156
6.11Memory Management in a Non-UNIX OS . . . . . . . . . . . . . . 157
7 Floating-Point Support 159
7.1 A Basic Description of Floating Point . . . . . . . . . . . . . . . . 159
7.2 The IEEE754 Standard and Its Background . . . . . . . . . . . . 160
7.3 How IEEE Floating-Point Numbers Are Stored . . . . . . . . . . . 162
7.3.1 IEEE Mantissa and Normalization . . . . . . . . . . . . . . 163
7.3.2 Reserved Exponent Values for Use with Strange Values . 164
7.3.3 FP Data Formats . . . . . . . . . . . . . . . . . . . . . . . . 164
7.4 MIPS Implementation of IEEE754 . . . . . . . . . . . . . . . . . . 166
7.4.1 Need for FP Trap Handler and Emulator in All MIPS CPUs 167
7.5 Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . . 167
7.5.1 Conventional Names and Uses of Floating-Point Registers 168
7.6 Floating-Point Exceptions/Interrupts . . . . . . . . . . . . . . . . 169
7.7 Floating-Point Control: The Control/Status Register . . . . . . . 170
7.8 Floating-Point Implementation/Revision Register . . . . . . . . . 172
7.9 Guide to FP Instructions . . . . . . . . . . . . . . . . . . . . . . . 173
7.9.1 Load/Store . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
7.9.2 Move between Registers . . . . . . . . . . . . . . . . . . . . 175
7.9.3 Three-Operand Arithmetic Operations . . . . . . . . . . . 176
7.9.4 Multiply-Add Operations . . . . . . . . . . . . . . . . . . . 177
7.9.5 Unary (Sign-Changing) Operations . . . . . . . . . . . . . 177
7.9.6 Conversion Operations . . . . . . . . . . . . . . . . . . . . 177
7.9.7 Conditional Branch and Test Instructions . . . . . . . . . 179
7.10Instruction Timing Requirements . . . . . . . . . . . . . . . . . . 180
7.11Instruction Timing for Speed . . . . . . . . . . . . . . . . . . . . . 181
7.12Initialization and Enabling on Demand . . . . . . . . . . . . . . . 182
7.13Floating-Point Emulation . . . . . . . . . . . . . . . . . . . . . . . 182
8 Complete Guide to the MIPS Instruction Set 185
8.1 A Simple Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
8.2 Assembler Mnemonics and What They Mean . . . . . . . . . . . 187
8.2.1 U and Non-U Mnemonics . . . . . . . . . . . . . . . . . . . 188
8.2.2 Divide Mnemonics . . . . . . . . . . . . . . . . . . . . . . . 189
8.2.3 Inventory of Instructions . . . . . . . . . . . . . . . . . . . 190
8.3 Floating-Point instructions . . . . . . . . . . . . . . . . . . . . . . 207
8.4 Peculiar Instructions and Their Purposes . . . . . . . . . . . . . 211
8.4.1 Load Left/Load Right: Unaligned Load and Store . . . . . 211
8.4.2 Load-Linked/Store-Conditional . . . . . . . . . . . . . . . 216
8.4.3 Conditional Move Instructions . . . . . . . . . . . . . . . . 217
8.4.4 Branch-Likely . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.4.5 Integer Multiply-Accumulate and Multiply-Add Instructions219
8.4.6 Floating-Point Multiply-Add Instructions . . . . . . . . . . 220
8.4.7 Multiple FP Condition Bits . . . . . . . . . . . . . . . . . . 220
8.4.8 Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.4.9 Sync: A Load/Store Barrier . . . . . . . . . . . . . . . . . . 221
8.5 Instruction Encodings . . . . . . . . . . . . . . . . . . . . . . . . . 222
8.5.1 Fields in the Instruction Encoding Table . . . . . . . . . . 223
8.5.2 Notes on the Instruction Encoding Table . . . . . . . . . . 224
8.5.3 Encodings and Simple Implementation . . . . . . . . . . . 233
8.6 Instructions by Functional Group . . . . . . . . . . . . . . . . . . 233
8.6.1 Nop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
8.6.2 Register/Register Moves . . . . . . . . . . . . . . . . . . . . 234
8.6.3 Load Constant . . . . . . . . . . . . . . . . . . . . . . . . . 234
8.6.4 Arithmetical/Logical . . . . . . . . . . . . . . . . . . . . . . 235
8.6.5 Integer Multiply, Divide, and Remainder . . . . . . . . . . 237
8.6.6 Integer Multiply-Accumulate . . . . . . . . . . . . . . . . . 238
8.6.7 Loads and Stores . . . . . . . . . . . . . . . . . . . . . . . . 239
8.6.8 Jumps, Subroutine Calls, and Branches . . . . . . . . . . 241
8.6.9 Breakpoint and Trap . . . . . . . . . . . . . . . . . . . . . 242
8.6.10CP0 functions . . . . . . . . . . . . . . . . . . . . . . . . . . 242
8.6.11Floating Point . . . . . . . . . . . . . . . . . . . . . . . . . . 243
8.6.12ATMizer-II Floating Point . . . . . . . . . . . . . . . . . . . 245
Assembler Language Programming 247
9.1 A Simple Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
9.2 Syntax Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
9.2.1 Layout, Delimiters, and Identifiers . . . . . . . . . . . . . . 251
9.3 General Rules for Instructions . . . . . . . . . . . . . . . . . . . . 252
9.3.1 Computational Instructions: Three-, Two-, and One-Register252
9.3.2 Regarding 64-Bit and 32-Bit Instructions . . . . . . . . . 253
9.4 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
9.4.1 Gp-Relative Addressing . . . . . . . . . . . . . . . . . . . . 255
9.5 Assembler Directives . . . . . . . . . . . . . . . . . . . . . . . . . 257
9.5.1 Selecting Sections . . . . . . . . . . . . . . . . . . . . . . . 257
9.5.2 Practical Program Layout Including Stack and Heap . . . 260
9.5.3 Data Definition and Alignment . . . . . . . . . . . . . . . . 260
9.5.4 Symbol-Binding Attributes . . . . . . . . . . . . . . . . . . 263
9.5.5 Function Directives . . . . . . . . . . . . . . . . . . . . . . 265
9.5.6 Assembler Control (.set) . . . . . . . . . . . . . . . . . . . . 267
9.5.7 Compiler/Debugger Support . . . . . . . . . . . . . . . . . 269
9.5.8 Additional Directives in SGI Assembly Language . . . . . 269
10C Programming on MIPS 271
10.1The Stack, Subroutine Linkage, and Parmeter Passing . . . . . . 272
10.2Stack Argument Structure . . . . . . . . . . . . . . . . . . . . . . 273
10.3Using Registers to Pass Arguments . . . . . . . . . . . . . . . . . 274
10.4Examples from the C Library . . . . . . . . . . . . . . . . . . . . . 275
10.5An Exotic Example: Passing Structures . . . . . . . . . . . . . . 276
10.6Passing a Variable Number of arguments . . . . . . . . . . . . . . 277
10.7Returning a Value from a Function . . . . . . . . . . . . . . . . . 278
10.8Evolving Register-Use Standards: SGI’s n32 and n64 . . . . . . 279
10.9Stack Layouts, Stack Frames, and Helping Debuggers . . . . . . 282
10.9.1Leaf Functions . . . . . . . . . . . . . . . . . . . . . . . . . 284
10.9.2Nonleaf Functions . . . . . . . . . . . . . . . . . . . . . . . 285
10.9.3Frame Pointers for More Complex Stack Requirements . . 288
10.10Variable Number of Arguments and stdargs . . . . . . . . . . . . 291
10.11Sharing Functions between Different Threads and Shared Library
Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
10.11.1Sharing Code in Single-Address-Space Systems . . . . . . 293
10.11.2Sharing Library Code in the MIPS ABI . . . . . . . . . . . 293
10.12An Introduction to Compiler Optimization . . . . . . . . . . . . . 296
10.12.1Common optimizations . . . . . . . . . . . . . . . . . . . . 297
10.12.2Optimizer Unfriendly Code and How to Avoid It . . . . . . 300
10.12.3The Limits of Optimization . . . . . . . . . . . . . . . . . . 300
10.13Hints about Device Access from C . . . . . . . . . . . . . . . . . . 301
10.13.1Using “volatile” to Inhibit Destructive Optimization . . . . 301
10.13.2Unaligned Data from C . . . . . . . . . . . . . . . . . . . . 303
11 Portability Considerations and C Code 305
11.1Porting to MIPS: A Checklist of Frequently Encountered Problems306
11.2An Idealized Porting Process . . . . . . . . . . . . . . . . . . . . . 308
11.2.1Three Porting Choices . . . . . . . . . . . . . . . . . . . . . 309
11.2.2Fixing Up Dependencies . . . . . . . . . . . . . . . . . . . . 310
11.2.3Isolating Nonportable Code . . . . . . . . . . . . . . . . . . 310
11.2.4When to Use Assembler . . . . . . . . . . . . . . . . . . . . 311
11.3Portable C and Language Standards . . . . . . . . . . . . . . . . 311
11.4C Library Functions and POSIX . . . . . . . . . . . . . . . . . . . 313
11.5Data Representations and Alignment . . . . . . . . . . . . . . . . 314
11.6Endianness: Words, Bytes, and Bit Order . . . . . . . . . . . . . 317
11.6.1Endianness and the Programmer . . . . . . . . . . . . . . 318
11.6.2Endianness: The Pictures and the Intellectual Problem . 319
11.6.3Endianness: The Hardware Problem . . . . . . . . . . . . 322
11.6.4Wiring a Connection between Opposite-Endian Camps . . 324
11.6.5Wiring an Endianness-Configurable Connection . . . . . 324
11.6.6Software to Cope with Both-Endianness of a MrPS CPU . 326
11.6.7Portability and Endianness-Independent Code . . . . . . 329
11.6.8Endianness and Foreign Data . . . . . . . . . . . . . . . . 329
11.6.9False Cures and False Prophets for Endianness Problems 330
11.7What Can Go Wrong with Caches and How to Stop It . . . . . . 331
11.7.1Cache Management and DMA Data . . . . . . . . . . . . . 332
11.7.2Cache Management and Writing Instructions . . . . . . . 333
11.7.3Cache Management and Uncache/Write-Through Data . 334
11.8Different Implementations of MIPS . . . . . . . . . . . . . . . . . 334
12 Software Example 337
12.1Starting Up MIPS . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
12.2MIPS Cache Management . . . . . . . . . . . . . . . . . . . . . . . 347
12.2.1Cache Operations: 32-Bit MIPS before Cache Instructions 348
12.2.2Cache Operations: After MIPS III and Cache Instructions 356
12.3MIPS Exception Handling . . . . . . . . . . . . . . . . . . . . . . . 368
12.3.1Xcption: What It Does for Programmers . . . . . . . . . . 368
12.3.2Xcption: C interface Code . . . . . . . . . . . . . . . . . . . 369
12.3.3Xcption: Low-Level Module . . . . . . . . . . . . . . . . . . 370
12.4MIPS Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
12.5Tuning for MIPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Instruction Timing and Optimization 389
A.1 Avoiding Hazards: Making Code Correct . . . . . . . . . . . . . . 389
A.2 Avoiding Interlocks to Increase Performance . . . . . . . . . . . . 390
A.3 Multiply Unit Hazards: Early Modification of hi and lo . . . . . . 391
A.4 Avoiding Coprocessor 0 Hazards: How Many nops? . . . . . . . . 392
A.5 Coprocessor 0 Instruction/Instruction Scheduling . . . . . . . . 394
A.6 Coprocessor 0 Flags and Instructions . . . . . . . . . . . . . . . . 395
Assembler Language Syntax 397
Object Code 403
C.1 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
C.2 Sections and Segments . . . . . . . . . . . . . . . . . . . . . . . . 405
C.3 ECOFF (RISC/OS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
C.3.1 File Header . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
C.3.2 Optional a.out Header . . . . . . . . . . . . . . . . . . . . . 409
C.3.3 Example Loader . . . . . . . . . . . . . . . . . . . . . . . . 410
C.3.4 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . 410
C.4 ELF (MIPS ABI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
C.4.1 File Header . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
C.4.2 Program Header . . . . . . . . . . . . . . . . . . . . . . . . 412
C.4.3 Example Loader . . . . . . . . . . . . . . . . . . . . . . . . 413
C.4.4 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . 414
C.5 Object Code Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
D Evolving MIPS 417
D.1 MIPS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
D.1.1 Special Encodings and Instructions in MIPS16 . . . . . . 418
D.1.2 MIPS16 Evaluated . . . . . . . . . . . . . . . . . . . . . . . 419
D.2 MIPS V/MDMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
D.2.1 Can Compilers Use Multimedia Instructions? . . . . . . . 421
D.2.2 Applications for MDMX . . . . . . . . . . . . . . . . . . . . 422
D.2.3 Applications for MIPS V . . . . . . . . . . . . . . . . . . . . 422
D.2.4 Likely Success of MDMX/MIPS V . . . . . . . . . . . . . . 423
MIPS Glossary 425

huadong1860

好书，谢谢了，一起努力吧

faersheng

这是一本好书。看到国内已经有人将它翻译出版，有中文版《透视MIPS处理》（See MIPS run）。

谢谢楼主了！

liuqingt001

原帖由 faersheng 于 2007-9-24 20:52 发表
这是一本好书。看到国内已经有人将它翻译出版，有中文版《透视MIPS处理》（See MIPS run）。

谢谢楼主了！

呵呵！

该书的中文版有另外一个版本，最近和该书英文版一起贴到该版，个人觉得翻译得还好，当然这些书籍都是入门的阶梯，最终还是应该去看mips芯片手册

"see mips run 中文版

see mips run linux(2nd edition)
看mips跑linux--mips体系结构剖析

D.Sweetman(斯维特曼) 著
J.Qu(屈建勤) 译
2007年7月27日
"

finalfantasy12

好书啊
正好需要

cjchang1

Thanks a lot !!!!!!!!!!!!!!

zwpinhzz

先顶一下

lbingbing

谢lz~~

qingyual

好书 谢谢了

xyx10021

不错，谢谢