芯原微电子(上海)社招（内部推荐）

dzkxybx

芯原微电子是一家芯片设计平台即服务（Silicon Platform as a Service，SiPaaS）提供商，为包含移动互联设备、数据中心、物联网、汽车、工业和医疗设备在内的广泛终端市场提供全面的系统级芯片（Soc）和系统级封装（SiP）解决方案。
目前公司发展不错。需求的岗位种类众多，包括ASIC 设计，验证，DFT，测试。GPU，视频，AR/AI研发，嵌入式，软件等。都在上海。

岗位和具体要求如下，有兴趣的同学可以联系我：dzkxybx@sina.com

ASIC Program Manager/Director

Engineer/Sr. Engineer of SoC Design

Sr. Engineer/Staff Engineer of SoC Verification

Engineer/Sr. Engineer of SoC FE Flow

Embedded Software Engineer/Sr. Engineer

Sr. Test Engineer

Staff Engineer of ISP Design

Sr. Staff/Staff Engineer of GPU Design

System Software Engineer

Sr. Staff/Staff Engineer of AI/AR ASIC Design

Sr. Computer Vision Software(Driver) Engineer

AI Chip CModel Engineer

1. Staff/Sr. Staff Engineer -- ISP ASIC Design
ISP 设计资深工程师
Responsibilities:
Design top-of-the-line graphics/ISP processors, including specification, architecture,
micro-architecture, implementation (using Verilog), and verification.
Requirements:
1. 3+ years hands-on experience.
2. Experience of leading a project from spec define to final release.
3. Programming skills in Verilog HDL.
4. Must be familiar with all stages of the ASIC design flow (including specification,
architecture, and design implementation).
5. Highly motivated and skillful at solving difficult technical problems.
6. Knowledge of computer graphics and low-power design techniques is a plus.
7. Experience of ISP design is a plus.
8. Experience of memory controller or bus fabric design is a plus



2. Staff/Sr. Staff Engineer -- GPU ASIC Design
GPU 设计资深工程师
Responsibilities:
Design top-of-the-line Graphics/Vision processors, including specification, architecture,
micro-architecture, implementation (using Verilog), and verification.
Expected skills:
1. 3+ years hands-on experience.
2. Programming skills in Verilog HDL.
3. Must be familiar with all stages of the ASIC design flow (including specification,
architecture, and design implementation).
4. Highly motivated and skillful at solving difficult technical problems.
5. Knowledge of computer graphics and low-power design techniques is a plus.
6. Experience of GPU design is a plus.
7. Experience of memory controller design or compression design is a plus.


3. Staff/Sr. Staff Engineer -- AI/AR ASIC Design
AR/AI 设计高级工程师  

Responsibilities:
Design top-of-the-line Vision process/Deep learning, including specification, architecture,
micro-architecture, implementation (using Verilog), and verification.
Requirements:
1. 3+ years hands-on experience.
2. Programming skills in Verilog HDL.
3. Must be familiar with all stages of the ASIC design flow (including specification,
architecture, and design implementation).
4. Highly motivated and skillful at solving difficult technical problems.
5. Knowledge of computing and low-power design techniques is a plus.
6. Experience of Vision process design or OpenCL VX is a plus.
7. Experience of CNN and deep learning design is a plus.

4. ASIC Program Manager/Director
ASIC 项目经理/总监
Responsibilities:
1. Manage and drive program decisions and schedules during pre-sale and post-sale stages;
2. Pivotal contact with development groups, sales/marketing teams and customers;
3. Provide central oversight over multiple aspects of multiple projects in terms of quality,
timeline, cost, scope, resource allocation and communication;
4. Ownership of project assessment over technology, schedule and cost;
5. Manage cross-functional groups and customer to insure success of the project;
6. Ensure project specifications and schedule compliance.
Requirements:
1. BSEE is required (MSEE is preferred) with 5+ years experience as an ASIC/IC design
leader/manager or project manager;
2. Leadership and problem-solving skills with strong presentation and communication skills;
3. Exposure to complete chip development lifecycle and entire design flow;
4. Understanding of chip deployment process (including packaging/testing/Software/board);
5. Track record of delivering projects on schedule is preferred;
6. Technical guidance skill set in various engineering field is preferred;
7. Solid interpersonal skill with fluent Mandarin and English;
8. Team player, motivated, organized and dedicated.

5. Embedded Software Engineer/Sr. Engineer
嵌入式软件开发工程师/高级工程师
Responsibilities:
1. Port Embedded Linux/Android for SoC chip, develop Linux driver and API for application;
2. Work with project members to determine system requirement, design prototyping and
support customers in product applications.
Requirements:
1. BSEE/CS 3+ years embedded software development experience in Linux;
2. Good knowledge/experience in ARM/PowerPC embedded system development,
PowerPC/ARM processor architecture and PowerPC/ARM Compiler;
3. Experienced in the drivers of CPU peripheral like LCD, NAND, flash, I2C, SPI, etc;
4. Experienced in embedded system design;
5. Working knowledge of the GNU tool chain for software development;
6. Android development experience and hardware related knowledge will be a plus;
7. Strong problem solving and analytical skills;
8. Self-motivated and good team player;
9. Good written and spoken English.

6. Title：Senior computer vision software(driver)engineer
资深计算视觉软件(驱动)工程师  

Responsibilities:

Develop computer vision driver stack, including Open VX, Android NN etc.

Optimize driver architecture to improve performance.

Work with arch team for design, profiling and verification.
Requirements:

Good C programming skill and produced production code.

Understand basic concepts in operation system and data structure/algorithm.

Worked on large software code bases.

Understand machine learning layer operations, vision algorithm and worked with hardware
acceleration.

At least 2 years related experience.

7. Engineer/Sr. Engineer of SoC Design
前端设计工程师/高级工程师
Responsibilities:
1. Play an important role in defining chip spec and devising chip architecture.
2. Develop challenging modules including module spec definition, macro architecture
design, RTL coding, simulation and synthesis.
3. Carry out chip level verification or chip integration/implementation.
4. Help junior engineers to solve technical issues.
5. Support customers regarding chip applications.
Requirements:
1. Bachelor degree or above in EE, 3+ years experience.
2. Good knowledge of some of the following general IP: CPU/DSP, AMBA,
DDR/SDRAM, video (HEVC, MIPI…), parallel/serial peripheral module, DMA,
interrupt, timer, GPIO.
3. Good skill in the field of digital circuit design, whole digital design flow and EDA tools;
4. Key member in at least one successfully silicon proven challenging project.
5. Fluent in both English and Chinese.
6. Self motivated, good communication skill and team work spirit


8. Sr. Engineer/Staff Engineer of SoC Verification
前端验证高级工程师/资深工程师
Responsibilities:
1. Understanding the expected functionality of designs.
2. Developing testing and regression plans.
3. Designing and developing verification environment.
4. Running RTL and gate-level simulations/regression.
5. Code/functional coverage development, analysis and closure.
Requirements:
1. Minimum of 3 years design/verification experience (test plan, test bench, assertions,
debugging designs, code coverage etc.).
2. Knowledge in ASIC/FPGA design process and verification tools/env ( UVM/OVM…).
3. Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
4. Scripting and automation skills (tcl, perl, makefile etc) a plus.
5. Familiar with C/C++.
6. Knowledge of DDR/Video/ARM/USB/PCIE , Low Power Verification with UPF and
design experience is a plus.
7. Experience in CPU/DSP verification, including test plan and test bench development,
test case development and test coverage assessment. and Knowledge of computer
architecture and micro-architecture (pipeline, out-of-order, cache) is a plus.
8. Additional qualifications include: Good IC verification skills and basic knowledge of
logic or circuit design, good communication and problem solving skills.
9. Independent and self-managing.


9. Engineer/Sr. Engineer of SoC FE Flow
前端流程工程师/高级工程师
Responsibilities:
1. Comprehend the SoC clock structure and working mode and prepare the SDC file for
SoC design.
2. Prepare the DFT plan for the SoC design.
3. SCAN/MBIST/BSD insertion and synthesize methodology for Flatten / Hierarchical
design.
4. Pre/Post simulation for test patterns.
5. Cooperate with timing engineer for timing signoff (STA).
6. Analog IP test implementation and simulation.
7. Support ATE engineer for chip testing debug, and analyze ATE log file to locate root
cause of failure.
8. Formal check of RTL and netlist.
Requirements:
1. Bachelor's degree or above, major in EE, CS or relevant.
2. Above 5years work experience to the one with Bachelor's degree and above 3years
with Master's degree is required for Senior Engineer position.
3. Skilled in SoC PPA, better for low power design.
4. Improve low test coverage to achieve higher coverage.
5. Skilled in csh/perl/tcl scripts.
6. Be familiar with concept of SoC and P&R physical implementation.
7. Fluent in both English and Chinese.
8. Good team work spirit.

10. Senior Test Engineer
资深测试工程师
Responsibilities:
1. Draw test plan for new product and discuss with designer about test feasibility;
2. Develop test program on various ATE platform for new product. Manage debug of test
program and hardware and meet product release schedule;
3. Support production and optimize program for test time reduction when volume ramp
up;
4. Support test chip development and characterization of VeriSilicon IPs.
Requirements:
1. Bachelor degree or above in EE with 3+ years of IC test experience is a must;
2. Familiar with one kind ATE tester among V50/J750/93K/D10/DX ,V93k platform and SoC
or mixed signal project development experience are preferred;
3. C/C++ and perl programming skills;
4. Familiar with pattern conversion tool Wavewizard;
5. Good spoken and written English skills;
6. Good communication skill and team work spirit;
7. Used to work in challenging cycle times.  


11. System Software Engineer

系统软件工程师
Responsibilities
1. Embedded software development based on ARM (and x86, PPC) Linux.
2. Window system integration for android, Linux, Wayland platforms.
3. Team work to accomplish projects, provide software driver and tests.
Requirements:
1. Bachelor degree in Computer Science, Communication, Electronic Engineering or
relevant.
2. 3+ years working experience
3. Solid knowledge in Linux kernel driver development. Master in C language.
4. Strong English written and verbal skills, available to read datasheet and technique SPEC.
5. Experience in Compute Graphics, DRM, KMS is a plus.
6. Proactive, energetic. excellent troubleshooting skills.

12. AI Chip Modeling Engineer
人工智能芯片建模工程师
Responsibilities:
1. Implement C-Model for HW accelerated algorithm and functionality of AI .
2. Develop tests, test plans, and testing infrastructure for to verify new algorithm and functionality and their
performance.
3. Co-work with RTL team, cross-validate model and RTL.
Requirements:
1. Master or PHD degree in Graphics, CS, EE, or Math, at least 3~5 years experience.
2. Strong C/C++ programming skill. Familiar with Windows Visual Studio programming, and Linux programming
environment.
3. Perl/Python programming skill is a plus.
4. Any experience on Deep-Learning/NN is good plus.
5. Any experience on DL frameworks, such as TensorFlow/Caffee, is good plus.
6. Strong background in computer architecture is a good plus.
7. Good written and spoken English.
8. Self motivated, team work, and good communication are a must.

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招1年的验证吗