为啥pt和icc的timing rpt 不一样，即使同一路径

edmilson28 · 发表于 2018-8-20 15:40:51

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本帖最后由 edmilson28 于 2018-8-28 11:06 编辑

除了环境设置不一样，还有没有其他可能性啊
=pt=======================================================================
  Startpoint: cj970_core_i1/carl_clk_i1_clk_mon_range_s_reg
            (rising edge-triggered flip-flop clocked by i_clk_osc)
  Endpoint: cj970_core_i1/config_i1_config_core_i1_cmb_i_current_state_reg_reg_1_
            (rising edge-triggered flip-flop clocked by i_clk_osc)
  Last common pin: CJ970_wbr_in_i1/U1459/Z
  Path Group: i_clk_osc
  Path Type: min

  Point                         Derate Incr    Path
  -----------------------------------------------------------
  clock i_clk_osc (rise edge)             0.00    0.00
  clock source latency                   0.00    0.00
  i_clk_osc (in)                         0.03 &    0.03 r
  CJ970_wbr_in_i1/U1459/A (MUX21HDP_3V)
                              0.95    0.00 &    0.03 r
  CJ970_wbr_in_i1/U1459/Z (MUX21HDP_3V)
                              0.95    1.38 &    1.41 r
  tcore_i1/t_func_i1/t_func_core_i1/U3/A (BFHDP_3V)
                              0.95    0.00 &    1.41 r
  tcore_i1/t_func_i1/t_func_core_i1/U3/Z (BFHDP_3V)
                              0.95    0.67 &    2.07 r
  tcore_i1/t_func_i1/t_func_core_i1/U4/A (BFHDP_3V)
                              0.95    0.00 &    2.07 r
  tcore_i1/t_func_i1/t_func_core_i1/U4/Z (BFHDP_3V)
                              0.95    0.40 &    2.47 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U19/A (BFHDP_3V)
                              0.95    0.00 &    2.47 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U19/Z (BFHDP_3V)
                              0.95    0.49 &    2.96 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U596/A (MUX21HD_3V)
                              0.95 -0.02 &    2.94 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U596/Z (MUX21HD_3V)
                              0.95    0.63 &    3.57 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U595/B (MUX21HDP_3V)
                              0.95    0.00 &    3.57 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U595/Z (MUX21HDP_3V)
                              0.95    0.59 &    4.16 r
  CTSIVHDX32_3V_G4B8I1/A (IVHDX5_3V)
                              0.95    0.00 &    4.16 r
  CTSIVHDX32_3V_G4B8I1/Z (IVHDX5_3V)
                              0.95    0.21 &    4.38 f
  CTSIVHD10C_3VLE_G4B7I1/A (IVHDX3_3V)
                              0.95    0.00 &    4.38 f
  CTSIVHD10C_3VLE_G4B7I1/Z (IVHDX3_3V)
                              0.95    0.23 &    4.61 r
  CTSIVHD8C_3VLE_G4B6I1/A (IVHDP_3V)
                              0.95    0.00 &    4.61 r
  CTSIVHD8C_3VLE_G4B6I1/Z (IVHDP_3V)
                              0.95    0.19 &    4.80 f
  CTSIVHDX32_3V_G4B5I1_1/A (IVHDP_3V)
                              0.95    0.00 &    4.80 f
  CTSIVHDX32_3V_G4B5I1_1/Z (IVHDP_3V)
                              0.95    0.15 &    4.95 r
  CTSBF2THD8C_3VLE_G4B3I1/A (BFHDX5_3V)
                              0.95    0.00 &    4.95 r
  CTSBF2THD8C_3VLE_G4B3I1/Z (BFHDX5_3V)
                              0.95    0.40 &    5.35 r
  CTSIVHD8C_3VLE_G4B2I1/A (IVHDX16_3V)
                              0.95    0.00 &    5.35 r
  CTSIVHD8C_3VLE_G4B2I1/Z (IVHDX16_3V)
                              0.95    0.16 &    5.51 f
  CTSIVHDX32_3V_G4B1I1/A (IVHDX32_3V)
                              0.95    0.00 &    5.51 f
  CTSIVHDX32_3V_G4B1I1/Z (IVHDX32_3V)
                              0.95    0.16 &    5.67 r
  cj970_core_i1/carl_clk_i1_clk_mon_range_s_reg/CP (FD2SQHDX05_3V)
                              0.95    0.00 &    5.67 r
  cj970_core_i1/carl_clk_i1_clk_mon_range_s_reg/Q (FD2SQHDX05_3V) <-
                              0.95    1.08 &    6.75 r
  cj970_core_i1/icc_clock9/A (DLY6HD_3V)
                              0.95 -0.07 &    6.69 r
  cj970_core_i1/icc_clock9/Z (DLY6HD_3V)
                              0.95    1.28 &    7.96 r
  cj970_core_i1/U883/A (NR3HDX05_3V)
                              0.95    0.00 &    7.96 r
  cj970_core_i1/U883/Z (NR3HDX05_3V)
                              0.95    0.46 &    8.43 f
  cj970_core_i1/U1479/A (AO17HD_3V)
                              0.95 -0.00 &    8.42 f
  cj970_core_i1/U1479/Z (AO17HD_3V)
                              0.95    0.46 &    8.88 r
  cj970_core_i1/U1486/A (AO6HD_3V)
                              0.95    0.00 &    8.88 r
  cj970_core_i1/U1486/Z (AO6HD_3V)
                              0.95    0.27 &    9.16 f
  cj970_core_i1/config_i1_config_core_i1_cmb_i_current_state_reg_reg_1_/D (FD2SQHDX05_3V)
                              0.95    0.00 &    9.16 f
  data arrival time                                  9.16

  clock i_clk_osc (rise edge)             0.00    0.00
  clock source latency                   0.00    0.00
  i_clk_osc (in)                         0.03 &    0.03 r
  CJ970_wbr_in_i1/U1459/A (MUX21HDP_3V)
                              1.05    0.00 &    0.03 r
  CJ970_wbr_in_i1/U1459/Z (MUX21HDP_3V)
                              1.05    1.53 &    1.56 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U579/B (MUX21HD_3V)
                              1.05    0.08 &    1.64 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U579/Z (MUX21HD_3V)
                              1.05    0.97 &    2.61 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U20/A (IVHDC_3VLE)
                              1.05    0.00 &    2.61 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U20/Z (IVHDC_3VLE)
                              1.05    0.30 &    2.92 f
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U21/A (IVHDX4_3V)
                              1.05    0.00 &    2.92 f
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U21/Z (IVHDX4_3V)
                              1.05    0.35 &    3.26 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U599/B (MUX21HDP_3V)
                              1.05    0.00 &    3.27 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U599/Z (MUX21HDP_3V)
                              1.05    0.72 &    3.99 r
  CTSIVHDX32_3V_G4B24I1/A (IVHD5C_3VLE)
                              1.05    0.00 &    3.99 r
  CTSIVHDX32_3V_G4B24I1/Z (IVHD5C_3VLE)
                              1.05    0.25 &    4.24 f
  CTSIVHDX16_3V_G4B23I1/A (IVHD8C_3VLE)
                              1.05    0.00 &    4.24 f
  CTSIVHDX16_3V_G4B23I1/Z (IVHD8C_3VLE)
                              1.05    0.27 &    4.51 r
  CTSIVHD8C_3VLE_G4B18I1/A (IVHD5C_3VLE)
                              1.05    0.01 &    4.52 r
  CTSIVHD8C_3VLE_G4B18I1/Z (IVHD5C_3VLE)
                              1.05    0.31 &    4.83 f
  CTSIVHDX32_3V_G4B17I1/A (IVHDX16_3V)
                              1.05    0.00 &    4.83 f
  CTSIVHDX32_3V_G4B17I1/Z (IVHDX16_3V)
                              1.05    0.26 &    5.09 r
  CTSIVHDX32_3V_G4B16I1/A (IVHDX32_3V)
                              1.05    0.01 &    5.10 r
  CTSIVHDX32_3V_G4B16I1/Z (IVHDX32_3V)
                              1.05    0.22 &    5.32 f
  CTSIVHDX32_3V_G4B15I2/A (IVHDX32_3V)
                              1.05    0.02 &    5.34 f
  CTSIVHDX32_3V_G4B15I2/Z (IVHDX32_3V)
                              1.05    0.11 &    5.45 r
  CTSIVHDX32_3V_G4B14I1/A (IVHD4C_3VLE)
                              1.05    0.00 &    5.45 r
  CTSIVHDX32_3V_G4B14I1/Z (IVHD4C_3VLE)
                              1.05    0.23 &    5.68 f
  CTSIVHDX32_3V_G4B13I1/A (IVHDX16_3V)
                              1.05    0.00 &    5.68 f
  CTSIVHDX32_3V_G4B13I1/Z (IVHDX16_3V)
                              1.05    0.23 &    5.91 r
  CTSIVHDX32_3V_G4B12I1/A (IVHDX32_3V)
                              1.05    0.01 &    5.92 r
  CTSIVHDX32_3V_G4B12I1/Z (IVHDX32_3V)
                              1.05    0.22 &    6.14 f
  CTSIVHDX32_3V_G4B11I4/A (IVHDX32_3V)
                              1.05    0.00 &    6.14 f
  CTSIVHDX32_3V_G4B11I4/Z (IVHDX32_3V)
                              1.05    0.18 &    6.32 r
  CTSIVHDX16_3V_G4B10I1/A (IVHDX8_3V)
                              1.05    0.00 &    6.32 r
  CTSIVHDX16_3V_G4B10I1/Z (IVHDX8_3V)
                              1.05    0.22 &    6.54 f
  CTSIVHDX32_3V_G4B9I1/A (IVHDX16_3V)
                              1.05    0.00 &    6.54 f
  CTSIVHDX32_3V_G4B9I1/Z (IVHDX16_3V)
                              1.05    0.19 &    6.73 r
  CTSIVHDX32_3V_G4B8I8/A (IVHDX16_3V)
                              1.05    0.00 &    6.73 r
  CTSIVHDX32_3V_G4B8I8/Z (IVHDX16_3V)
                              1.05    0.17 &    6.90 f
  CTSIVHDX32_3V_G4B7I4/A (IVHDX16_3V)
                              1.05    0.00 &    6.90 f
  CTSIVHDX32_3V_G4B7I4/Z (IVHDX16_3V)
                              1.05    0.15 &    7.05 r
  CTSIVHDX32_3V_G4B6I1/A (IVHDX5_3V)
                              1.05    0.00 &    7.05 r
  CTSIVHDX32_3V_G4B6I1/Z (IVHDX5_3V)
                              1.05    0.24 &    7.29 f
  CTSIVHDX32_3V_G4B5I6/A (IVHDX16_3V)
                              1.05    0.00 &    7.29 f
  CTSIVHDX32_3V_G4B5I6/Z (IVHDX16_3V)
                              1.05    0.23 &    7.53 r
  CTSIVHDX16_3V_G4B4I3/A (IVHDP_3V)
                              1.05    0.00 &    7.53 r
  CTSIVHDX16_3V_G4B4I3/Z (IVHDP_3V)
                              1.05    0.28 &    7.81 f
  CTSIVHDX32_3V_G4B3I3/A (IVHDX5_3V)
                              1.05    0.00 &    7.81 f
  CTSIVHDX32_3V_G4B3I3/Z (IVHDX5_3V)
                              1.05    0.25 &    8.05 r
  CTSIVHDX32_3V_G4B2I32/A (IVHDX8_3V)
                              1.05    0.00 &    8.06 r
  CTSIVHDX32_3V_G4B2I32/Z (IVHDX8_3V)
                              1.05    0.38 &    8.43 f
  CTSIVHDX32_3V_G4B1I9/A (IVHDX16_3V)
                              1.05    0.00 &    8.44 f
  CTSIVHDX32_3V_G4B1I9/Z (IVHDX16_3V)
                              1.05    0.32 &    8.76 r
  cj970_core_i1/config_i1_config_core_i1_cmb_i_current_state_reg_reg_1_/CP (FD2SQHDX05_3V)
                              1.05    0.00 &    8.76 r
  clock reconvergence pessimism          -0.16    8.60
  library hold time             1.00    0.02    8.62
  data required time                               8.62
  -----------------------------------------------------------
  data required time                               8.62
  data arrival time                               -9.16
  -----------------------------------------------------------
  slack (MET)                                        0.53

****************************************
Report : design
Design : cj970_dig
Version: L-2016.06-SP3
Date : Thu Aug 23 09:42:41 2018
****************************************

Design Attribute                      Value
---------------------------------------------------------------------------
Operating Conditions:
  analysis_type                         on_chip_variation
  operating_condition_min_name          wc_2.70V_175C
  process_min                         1.2
  temperature_min                      175
  voltage_min                         2.7
  tree_type_min                         balanced_case

  operating_condition_max_name          wc_2.70V_175C
  process_max                         1.2
  temperature_max                      175
  voltage_max                         2.7
  tree_type_max                         balanced_case

Wire Load:                            (use report_wire_load for more information)
  wire_load_mode                      enclosed
  wire_load_model_max                   area_624Kto936K
  wire_load_model_library_max          BCD900016HD3V3SL_wc_2.70V_175C
  wire_load_selection_type_max          automatic-by-area
  wire_load_model_min                   area_624Kto936K
  wire_load_model_library_min          BCD900016HD3V3SL_wc_2.70V_175C
  wire_load_selection_type_min          automatic-by-area
  wire_load_selection_group_max       default_by_area
  wire_load_selection_group_min       default_by_area
  wire_load_min_block_size             0

Design Rules:
  max_capacitance                      --
  min_capacitance                      --
  max_fanout                            --
  max_transition                      --
  static_integrity                      --
  dynamic_integrity                   --
  delay_penalty_limit                   --
  max_area                            0

Timing Ranges:
  early_rise_clk_net_derate_factor    0.95
  early_fall_clk_net_derate_factor    0.95
  early_rise_data_net_derate_factor    0.95
  early_fall_data_net_derate_factor    0.95
  early_rise_clk_net_delta_derate_factor 0.95
  early_fall_clk_net_delta_derate_factor 0.95
  early_rise_data_net_delta_derate_factor
                                       0.95
  early_fall_data_net_delta_derate_factor
                                       0.95
  early_rise_clk_cell_derate_factor    0.95
  early_fall_clk_cell_derate_factor    0.95
  early_rise_data_cell_derate_factor    0.95
  early_fall_data_cell_derate_factor    0.95
  early_rise_cell_check_derate_factor --
  early_fall_cell_check_derate_factor --
  late_rise_clk_net_derate_factor       1.05
  late_fall_clk_net_derate_factor       1.05
  late_rise_data_net_derate_factor    1.05
  late_fall_data_net_derate_factor    1.05
  late_rise_clk_net_delta_derate_factor  1.05
  late_fall_clk_net_delta_derate_factor  1.05
  late_rise_data_net_delta_derate_factor 1.05
  late_fall_data_net_delta_derate_factor 1.05
  late_rise_clk_cell_derate_factor    1.05
  late_fall_clk_cell_derate_factor    1.05
  late_rise_data_cell_derate_factor    1.05
  late_fall_data_cell_derate_factor    1.05
  late_rise_cell_check_derate_factor    --
  late_fall_cell_check_derate_factor    --

Pin Input Delays:
None specified.

Pin Output Delays:
None specified.
Fast Analysis:                         disabled

=icc=============================================================
  Startpoint: cj970_core_i1/carl_clk_i1_clk_mon_range_s_reg
            (rising edge-triggered flip-flop clocked by i_clk_osc)
  Endpoint: cj970_core_i1/config_i1_config_core_i1_cmb_i_current_state_reg_reg_1_
            (rising edge-triggered flip-flop clocked by i_clk_osc)
  Last common pin: CJ970_wbr_in_i1/U1459/Z
  Path Group: i_clk_osc
  Path Type: min

  Point                         Derate Incr    Path
  -----------------------------------------------------------
  clock i_clk_osc (rise edge)             0.00    0.00
  clock source latency                   0.00    0.00
  i_clk_osc (in)                         0.03 &    0.03 r
  CJ970_wbr_in_i1/U1459/A (MUX21HDP_3V)
                              0.95    0.00 &    0.03 r
  CJ970_wbr_in_i1/U1459/Z (MUX21HDP_3V)
                              0.95    1.38 &    1.41 r
  tcore_i1/t_func_i1/t_func_core_i1/U3/A (BFHDP_3V)
                              0.95    0.00 &    1.41 r
  tcore_i1/t_func_i1/t_func_core_i1/U3/Z (BFHDP_3V)
                              0.95    0.67 &    2.07 r
  tcore_i1/t_func_i1/t_func_core_i1/U4/A (BFHDP_3V)
                              0.95    0.00 &    2.07 r
  tcore_i1/t_func_i1/t_func_core_i1/U4/Z (BFHDP_3V)
                              0.95    0.40 &    2.47 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U19/A (BFHDP_3V)
                              0.95    0.00 &    2.47 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U19/Z (BFHDP_3V)
                              0.95    0.49 &    2.96 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U596/A (MUX21HD_3V)
                              0.95 -0.02 &    2.94 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U596/Z (MUX21HD_3V)
                              0.95    0.63 &    3.57 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U595/B (MUX21HDP_3V)
                              0.95    0.00 &    3.57 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U595/Z (MUX21HDP_3V)
                              0.95    0.59 &    4.16 r
  CTSIVHDX32_3V_G4B8I1/A (IVHDX5_3V)
                              0.95    0.00 &    4.16 r
  CTSIVHDX32_3V_G4B8I1/Z (IVHDX5_3V)
                              0.95    0.21 &    4.38 f
  CTSIVHD10C_3VLE_G4B7I1/A (IVHDX3_3V)
                              0.95    0.00 &    4.38 f
  CTSIVHD10C_3VLE_G4B7I1/Z (IVHDX3_3V)
                              0.95    0.23 &    4.61 r
  CTSIVHD8C_3VLE_G4B6I1/A (IVHDP_3V)
                              0.95    0.00 &    4.61 r
  CTSIVHD8C_3VLE_G4B6I1/Z (IVHDP_3V)
                              0.95    0.19 &    4.80 f
  CTSIVHDX32_3V_G4B5I1_1/A (IVHDP_3V)
                              0.95    0.00 &    4.80 f
  CTSIVHDX32_3V_G4B5I1_1/Z (IVHDP_3V)
                              0.95    0.15 &    4.95 r
  CTSBF2THD8C_3VLE_G4B3I1/A (BFHDX5_3V)
                              0.95    0.00 &    4.95 r
  CTSBF2THD8C_3VLE_G4B3I1/Z (BFHDX5_3V)
                              0.95    0.40 &    5.35 r
  CTSIVHD8C_3VLE_G4B2I1/A (IVHDX16_3V)
                              0.95    0.00 &    5.35 r
  CTSIVHD8C_3VLE_G4B2I1/Z (IVHDX16_3V)
                              0.95    0.16 &    5.51 f
  CTSIVHDX32_3V_G4B1I1/A (IVHDX32_3V)
                              0.95    0.00 &    5.51 f
  CTSIVHDX32_3V_G4B1I1/Z (IVHDX32_3V)
                              0.95    0.16 &    5.67 r
  cj970_core_i1/carl_clk_i1_clk_mon_range_s_reg/CP (FD2SQHDX05_3V)
                              0.95    0.00 &    5.67 r
  cj970_core_i1/carl_clk_i1_clk_mon_range_s_reg/Q (FD2SQHDX05_3V) <-
                              0.95    1.08 &    6.75 r
  cj970_core_i1/icc_clock9/A (DLY6HD_3V)
                              0.95 -0.07 &    6.69 r
  cj970_core_i1/icc_clock9/Z (DLY6HD_3V)
                              0.95    1.28 &    7.96 r
  cj970_core_i1/U883/A (NR3HDX05_3V)
                              0.95    0.00 &    7.96 r
  cj970_core_i1/U883/Z (NR3HDX05_3V)
                              0.95    0.46 &    8.43 f
  cj970_core_i1/U1479/A (AO17HD_3V)
                              0.95 -0.00 &    8.42 f
  cj970_core_i1/U1479/Z (AO17HD_3V)
                              0.95    0.46 &    8.88 r
  cj970_core_i1/U1486/A (AO6HD_3V)
                              0.95    0.00 &    8.88 r
  cj970_core_i1/U1486/Z (AO6HD_3V)
                              0.95    0.27 &    9.16 f
  cj970_core_i1/config_i1_config_core_i1_cmb_i_current_state_reg_reg_1_/D (FD2SQHDX05_3V)
                              0.95    0.00 &    9.16 f
  data arrival time                                  9.16

  clock i_clk_osc (rise edge)             0.00    0.00
  clock source latency                   0.00    0.00
  i_clk_osc (in)                         0.03 &    0.03 r
  CJ970_wbr_in_i1/U1459/A (MUX21HDP_3V)
                              1.05    0.00 &    0.03 r
  CJ970_wbr_in_i1/U1459/Z (MUX21HDP_3V)
                              1.05    1.53 &    1.56 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U579/B (MUX21HD_3V)
                              1.05    0.08 &    1.64 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U579/Z (MUX21HD_3V)
                              1.05    0.97 &    2.61 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U20/A (IVHDC_3VLE)
                              1.05    0.00 &    2.61 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U20/Z (IVHDC_3VLE)
                              1.05    0.30 &    2.92 f
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U21/A (IVHDX4_3V)
                              1.05    0.00 &    2.92 f
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U21/Z (IVHDX4_3V)
                              1.05    0.35 &    3.26 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U599/B (MUX21HDP_3V)
                              1.05    0.00 &    3.27 r
  tcore_i1/t_func_i1/t_func_core_i1/tmux_i1/U599/Z (MUX21HDP_3V)
                              1.05    0.72 &    3.99 r
  CTSIVHDX32_3V_G4B24I1/A (IVHD5C_3VLE)
                              1.05    0.00 &    3.99 r
  CTSIVHDX32_3V_G4B24I1/Z (IVHD5C_3VLE)
                              1.05    0.25 &    4.24 f
  CTSIVHDX16_3V_G4B23I1/A (IVHD8C_3VLE)
                              1.05    0.00 &    4.24 f
  CTSIVHDX16_3V_G4B23I1/Z (IVHD8C_3VLE)
                              1.05    0.27 &    4.51 r
  CTSIVHD8C_3VLE_G4B18I1/A (IVHD5C_3VLE)
                              1.05    0.01 &    4.52 r
  CTSIVHD8C_3VLE_G4B18I1/Z (IVHD5C_3VLE)
                              1.05    0.31 &    4.83 f
  CTSIVHDX32_3V_G4B17I1/A (IVHDX16_3V)
                              1.05    0.00 &    4.83 f
  CTSIVHDX32_3V_G4B17I1/Z (IVHDX16_3V)
                              1.05    0.26 &    5.09 r
  CTSIVHDX32_3V_G4B16I1/A (IVHDX32_3V)
                              1.05    0.01 &    5.10 r
  CTSIVHDX32_3V_G4B16I1/Z (IVHDX32_3V)
                              1.05    0.22 &    5.32 f
  CTSIVHDX32_3V_G4B15I2/A (IVHDX32_3V)
                              1.05    0.02 &    5.34 f
  CTSIVHDX32_3V_G4B15I2/Z (IVHDX32_3V)
                              1.05    0.11 &    5.45 r
  CTSIVHDX32_3V_G4B14I1/A (IVHD4C_3VLE)
                              1.05    0.00 &    5.45 r
  CTSIVHDX32_3V_G4B14I1/Z (IVHD4C_3VLE)
                              1.05    0.23 &    5.68 f
  CTSIVHDX32_3V_G4B13I1/A (IVHDX16_3V)
                              1.05    0.00 &    5.68 f
  CTSIVHDX32_3V_G4B13I1/Z (IVHDX16_3V)
                              1.05    0.23 &    5.91 r
  CTSIVHDX32_3V_G4B12I1/A (IVHDX32_3V)
                              1.05    0.01 &    5.92 r
  CTSIVHDX32_3V_G4B12I1/Z (IVHDX32_3V)
                              1.05    0.22 &    6.14 f
  CTSIVHDX32_3V_G4B11I4/A (IVHDX32_3V)
                              1.05    0.00 &    6.14 f
  CTSIVHDX32_3V_G4B11I4/Z (IVHDX32_3V)
                              1.05    0.18 &    6.32 r
  CTSIVHDX16_3V_G4B10I1/A (IVHDX8_3V)
                              1.05    0.00 &    6.32 r
  CTSIVHDX16_3V_G4B10I1/Z (IVHDX8_3V)
                              1.05    0.22 &    6.54 f
  CTSIVHDX32_3V_G4B9I1/A (IVHDX16_3V)
                              1.05    0.00 &    6.54 f
  CTSIVHDX32_3V_G4B9I1/Z (IVHDX16_3V)
                              1.05    0.19 &    6.73 r
  CTSIVHDX32_3V_G4B8I8/A (IVHDX16_3V)
                              1.05    0.00 &    6.73 r
  CTSIVHDX32_3V_G4B8I8/Z (IVHDX16_3V)
                              1.05    0.17 &    6.90 f
  CTSIVHDX32_3V_G4B7I4/A (IVHDX16_3V)
                              1.05    0.00 &    6.90 f
  CTSIVHDX32_3V_G4B7I4/Z (IVHDX16_3V)
                              1.05    0.15 &    7.05 r
  CTSIVHDX32_3V_G4B6I1/A (IVHDX5_3V)
                              1.05    0.00 &    7.05 r
  CTSIVHDX32_3V_G4B6I1/Z (IVHDX5_3V)
                              1.05    0.24 &    7.29 f
  CTSIVHDX32_3V_G4B5I6/A (IVHDX16_3V)
                              1.05    0.00 &    7.29 f
  CTSIVHDX32_3V_G4B5I6/Z (IVHDX16_3V)
                              1.05    0.23 &    7.53 r
  CTSIVHDX16_3V_G4B4I3/A (IVHDP_3V)
                              1.05    0.00 &    7.53 r
  CTSIVHDX16_3V_G4B4I3/Z (IVHDP_3V)
                              1.05    0.28 &    7.81 f
  CTSIVHDX32_3V_G4B3I3/A (IVHDX5_3V)
                              1.05    0.00 &    7.81 f
  CTSIVHDX32_3V_G4B3I3/Z (IVHDX5_3V)
                              1.05    0.25 &    8.05 r
  CTSIVHDX32_3V_G4B2I32/A (IVHDX8_3V)
                              1.05    0.00 &    8.06 r
  CTSIVHDX32_3V_G4B2I32/Z (IVHDX8_3V)
                              1.05    0.38 &    8.43 f
  CTSIVHDX32_3V_G4B1I9/A (IVHDX16_3V)
                              1.05    0.00 &    8.44 f
  CTSIVHDX32_3V_G4B1I9/Z (IVHDX16_3V)
                              1.05    0.32 &    8.76 r
  cj970_core_i1/config_i1_config_core_i1_cmb_i_current_state_reg_reg_1_/CP (FD2SQHDX05_3V)
                              1.05    0.00 &    8.76 r
  clock reconvergence pessimism          -0.16    8.60
  library hold time             1.00    0.02    8.62
  data required time                               8.62
  -----------------------------------------------------------
  data required time                               8.62
  data arrival time                               -9.16
  -----------------------------------------------------------
  slack (MET)                                        0.53

****************************************
Report : design
Design : cj970_dig
Version: L-2016.06-SP3
Date : Thu Aug 23 09:42:41 2018
****************************************

Design Attribute                      Value
---------------------------------------------------------------------------
Operating Conditions:
  analysis_type                         on_chip_variation
  operating_condition_min_name          wc_2.70V_175C
  process_min                         1.2
  temperature_min                      175
  voltage_min                         2.7
  tree_type_min                         balanced_case

  operating_condition_max_name          wc_2.70V_175C
  process_max                         1.2
  temperature_max                      175
  voltage_max                         2.7
  tree_type_max                         balanced_case

Wire Load:                            (use report_wire_load for more information)
  wire_load_mode                      enclosed
  wire_load_model_max                   area_624Kto936K
  wire_load_model_library_max          BCD900016HD3V3SL_wc_2.70V_175C
  wire_load_selection_type_max          automatic-by-area
  wire_load_model_min                   area_624Kto936K
  wire_load_model_library_min          BCD900016HD3V3SL_wc_2.70V_175C
  wire_load_selection_type_min          automatic-by-area
  wire_load_selection_group_max       default_by_area
  wire_load_selection_group_min       default_by_area
  wire_load_min_block_size             0

Design Rules:
  max_capacitance                      --
  min_capacitance                      --
  max_fanout                            --
  max_transition                      --
  static_integrity                      --
  dynamic_integrity                   --
  delay_penalty_limit                   --
  max_area                            0

Timing Ranges:
  early_rise_clk_net_derate_factor    0.95
  early_fall_clk_net_derate_factor    0.95
  early_rise_data_net_derate_factor    0.95
  early_fall_data_net_derate_factor    0.95
  early_rise_clk_net_delta_derate_factor 0.95
  early_fall_clk_net_delta_derate_factor 0.95
  early_rise_data_net_delta_derate_factor
                                       0.95
  early_fall_data_net_delta_derate_factor
                                       0.95
  early_rise_clk_cell_derate_factor    0.95
  early_fall_clk_cell_derate_factor    0.95
  early_rise_data_cell_derate_factor    0.95
  early_fall_data_cell_derate_factor    0.95
  early_rise_cell_check_derate_factor --
  early_fall_cell_check_derate_factor --
  late_rise_clk_net_derate_factor       1.05
  late_fall_clk_net_derate_factor       1.05
  late_rise_data_net_derate_factor    1.05
  late_fall_data_net_derate_factor    1.05
  late_rise_clk_net_delta_derate_factor  1.05
  late_fall_clk_net_delta_derate_factor  1.05
  late_rise_data_net_delta_derate_factor 1.05
  late_fall_data_net_delta_derate_factor 1.05
  late_rise_clk_cell_derate_factor    1.05
  late_fall_clk_cell_derate_factor    1.05
  late_rise_data_cell_derate_factor    1.05
  late_fall_data_cell_derate_factor    1.05
  late_rise_cell_check_derate_factor    --
  late_fall_cell_check_derate_factor    --

Pin Input Delays:
None specified.

Pin Output Delays:
None specified.
Fast Analysis:                         disabled

besttian · 发表于 2018-8-24 21:20:21

不同的mode？
不同的RC抽取？
不同的delay calculator？

[求助] 为啥pt和icc的timing rpt 不一样，即使同一路径

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