柯明道教授2007年最新ESD论文！

semico_ljj

Ming-Dou Ker 柯明道教授2007年最新ESD论文！

Overview on ESD protection design for mixed-voltage I/O interfaces
with high-voltage-tolerant power-rail ESD clamp circuits
in low-voltage thin-oxide CMOS technology


Abstract
Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-achip
(SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should
meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design
concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS
transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail
ESD clamp circuits are presented and discussed.
 2006 Elsevier Ltd. All rights reserved.

semico_ljj

柯明道！！！

zhxdoctor

xiexie  louzhu!!!

yangxh1985

好东东啊，谢谢

soexcite

    thanks for share

zhxdoctor

谢谢楼主了！

davis_chen

谢谢楼主了 这个方面的资料不是恨多啊

6789

早有人发过了吧

semico_ljj

who 发的？

123451

Thanks very much.