verilog-xl后仿真的错误

sunsibing

我的思路是这样的：
(1)芯片综合后用 write_sdf  -version 2.1 sdf_path + digital.sdf
部分文件为:
(CELL
  (CELLTYPE "AH01D1")
  (INSTANCE wdtreg/add_22/U1_1_6)
  (DELAY
    (ABSOLUTE
    (IOPATH A C (0.581:0.581:0.581) (0.462:0.471:0.471))
    (IOPATH B C (0.552:0.552:0.552) (0.390:0.393:0.393))
    (IOPATH (posedge A) S (0.879:0.879:0.879) (0.940:0.940:0.940))
    (IOPATH (negedge A) S (0.859:0.868:0.868) (0.923:0.932:0.932))
    (IOPATH (posedge B) S (0.583:0.583:0.583) (0.650:0.650:0.650))
    (IOPATH (negedge B) S (0.558:0.561:0.561) (0.623:0.627:0.627))
    )
  )
网表中能够找到这个单元。
(2)反标sdf在verilog-xl进行仿真,因我的综合模块digital只是其中一部分,仿真时需要其他未综合的辅助模块bottom1,top2,其中bottom1和digital合并成一个模块top1,所以我的test文件中包含两个模块top1(bottom1和digital)和top2,在test文件中用下面语句进行反标:
initial begin
   $sdf_annotate("digital.sdf",top1.digital);
end
(3) 启动verilog-xl仿真,提示错误为:
digital.sdf  L13495: SDFA Error: Could not find path A to C in instance test.top1.digital.wdtreg.add_22.U1_1_6
.....
不知这样的错误如何解释,望大家指点,万分感谢!

appleyuchi2

把代码都列出来