CMOS PLL Synthesizers Analysis and Design

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CMOS PLL Synthesizers Analysis and Design

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List of Acronyms and Symbols
Preface
1 Introduction
1.1 MOTIVATION
1.2 SUMMAROYF BOOK
1.3 BOOK ORGANIZATION
REFERENCES
2 Frequency Synthesizer for Wireless Applications
2.1 DEFINITIOANN D CHARACTERISTICS
2.2 PHASEN OISE AND TIMING JITTER
2.2.1 Phase noise and spurious tone ............................................ 8
2.2.2 Timing jitter. ... ... .. .. .. .. .. .. .. .. .. .. . .. . ... .. . . .. . . . . . . . . . . . . . . . 1 1
2.3 IMPLEMENTATION OF FREQUENCY SYNTHESIZER 14
2.3.1 Direct analog frequency synthesizer ................................. 14
2.3.2 Direct digital frequency synthesizer .... . .. .. .. .. .. .. .. .. .. .. ... .. .. .. 15
2.3.3 PLL-based frequency synthesizer.. .. .... .. .. .. .. .. .. .. .. .. .. . . . . 1 6
2.3.4 DLL-based frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.3.5 Hybrid frequency synthesizer .. .. .. .. . . .. .. .. .. .. .. .. .. .. .. .. .. .. ... . . 21
2.3.6 Summary and comparison of synthesizers ......................... 21
2.4 FREQUENCSYYN THESIZER FOR WIRELESS TRANSCEIVERS 22
2.5 OTHER APPLICATIONS OF PLL AND FREQUENCY SYNTHESIZER 24
REFERENCES 26
3 PLL Frequency Synthesizer 3 1
3.1 PLL FREQUENCY SYNTHESIZER BASICS 3 1
3.1.1 Basic building blocks of charge-pump PLL ...................... 31
3.1.2 Continuous-time linear phase analysis ..............................3 4
3.1.3 Locking time ...................................................................... 44
3.1.4 Tracking and acquisition. ................................................... 56
3.2 FAST-LOCKINTGEC HNIQUES 5 8
3.2.1 Bandwidth gear-shifting .................................................... 58
3.2.2 VCO pre-tuning ................................................................. 60
3.3 DISCRETE-TIMAEN ALYSIS AND NONLINEAR MODELING 60
3.3.1 z-domain transfer function and stability analysis .............. 60
3.3.2 Nonlinear dynamic behavior modeling .............................. 62
3.4 DESIGNE XAMPLE: 2.4GHz INTEGER-N PLL FOR BLUETOOTH6 2
REFERENCES 65
4 ZA Fractional-N PLL Synthesizer 69
4.1 CA FRACTIONALF-NRE QUENCY SYNTHESIZER 69
4.1.1 CA quantization noise to phase noise mapping .................. 70
4.1.2 CA quantization noise to timing jitter mapping ................. 73
4.2 A COMPARATIVE STUDY OF DIGITAL ZA MODULATORS 7 3
4.2.1 Design considerations ........................................................ 73
4.2.2 Four types of digital CA modulators ..................................7 4
4.2.3 Summary of comparative study ........................................8 7
4.3 OTHERA PPLICATIONS OF ZA-PLL 90
4.3.1 Direct digital modulation ...................................................9 0
4.3.2 Frequency-to-digital conversion ........................................9 1
4.4 MODELINAGN D SIMULATION OF CA-PLL 92
4.5 DESIGNE XAMPLE: 900MHZ ZA-PLL FOR GSM 95
REFERENCES 98
5 Enhanced Phase Switching Prescaler 103
5.1 PRESCALEARR CHITECTURE 103
5.1.1 Conventional prescaler .................................................... 103
5.1.2 Phase switching prescaler ................................................ 105
5.1.3 Injection-locked prescaler ................................................ 107
5.1.4 Summary and comparison of prescalers .......................... 107
5.2 ENHANCEPDH ASE-SWITCHING PRESCALER 108
5.3 CIRCUITDE SIGN AND SIMULATION RESULTS 110
5.3.1 Eight 45'-spaced phases generation ................................ 110
5.3.2 8-to-1 multiplexer ............................................................ 111
5.3.3 Switching control circuit .................................................. 112
5.3.4 Asynchronous frequency divider ..................................... 113
5.4 DELAYB UDGET IN THE SWITCHING CONTROL LOOP 115
5.5 SPURSD UE TO NONIDEAL 45' PHASE SPACING
REFERENCES
6 Loop Filter With Capacitance Multiplier 127
6.1 LOOP FILTER ARCHITECTURE 127
6.1.1 Passive loop filter ........................................................... 127
6.1.2 Dual-path loop filter ......................................................... 128
6.1.3 Sample-reset loop filter.. .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. . . . . . . . . 13 1
6.1.4 Other loop filter architectures ........................................ 133
6.1.5 Summary and comparison of loop filters ......................... 137
6.2 LOOP FILTER AND CHARGE-PUMP NOISE MAPPING 138
6.3 LOOP FILTER WITH CAPACITANCE MULTIPLIER 141
6.3.1 Third-order passive loop filter ......................................... 141
6.3.2 Capacitance multiplier. .. .. .. .. .. .. .. ...... ...... . .. .. .. .. .. .. . . . . . . 142
6.3.3 Simulation of loop filter with capacitance multiplier ...... 145
6.3.4 Noise consideration ..... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . 148
REFERENCES 149
7 Other Building Blocks of PLL 151
7.1 VCO 151
7.1.1 LC-VCO .......................................................................... 151
7.1.2 Varactor ... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . 152
7.1.3 Inductor ... .. .. .. . .. . .. . .. .. .. .. .. .. .. .. . . . , . . . . . . . . , . . . , . . . . . . . . 155
7.1.4 VCO phase noise ............................................................. 156
7.1.5 Layout ............................................................................. 161
7.2 PHASE-FREQUENCY DETECTOR 162
7.3 CHARGE-PUMP 164
7.3.1 Reference spur .... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . 1 6 4
7.3.2 Charge pump architectures .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1
7.4 PROGRAMMABLE DIVIDER 173
7.5 DIGITAL ZA MODULATOR 176
7.6 CHIP LAYOUT 176
REFERENCES 178
8 Prototype Measurement Results
8.1 PRESCALEMRE ASUREMENT
8.2 LOOP FILTER MEASUREMENT
8.3 PLL MEASUREMENT
REFERENCES
9 Conclusions
Appendix

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