CMOS Current Amplifiers: Speed versus Nonlinearity

basildy

1 Introduction to current-mode circuit techniques 1
1.1 Development of integration technologies . . . . . . . . . . . . . . . . 1
1.2 Motivation for current-mode circuit design . . . . . . . . . . . . . . . 2
1.3 Evolution of current-mode building blocks . . . . . . . . . . . . . . . 3
1.4 Adjoint principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Scope of this book . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6 Contributions by the author . . . . . . . . . . . . . . . . . . . . . . . 8
2 Basic current amplifiers 15
2.1 Current-mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.1 Nonidealities due to the channel length modulation . . . . . . 17
2.1.2 Nonidealities due to the threshold voltage mismatch . . . . . 20
2.1.3 High frequency nonidealities . . . . . . . . . . . . . . . . . 22
Linear effects . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Nonlinear effects . . . . . . . . . . . . . . . . . . . . . . . . 24
2.1.4 Distortion reduction methods . . . . . . . . . . . . . . . . . . 30
Transconductance linearisation . . . . . . . . . . . . . . . . . 30
Nonlinear current reduction . . . . . . . . . . . . . . . . . . 31
Nonlinear current cancellation . . . . . . . . . . . . . . . . . 31
2.1.5 Noise and dynamic range . . . . . . . . . . . . . . . . . . . . 33
2.1.6 Other mirror topologies . . . . . . . . . . . . . . . . . . . . 36
Accurate current-mirror topologies for large signal amplitudes 36
Resistively compensated mirror . . . . . . . . . . . . . . . . 38
2.2 Current buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.2.1 Linear nonidealities . . . . . . . . . . . . . . . . . . . . . . . 41
2.2.2 Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.2.3 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.2.4 Alternative topologies . . . . . . . . . . . . . . . . . . . . . 44
3 Open-loop current amplifiers 49
3.1 First generation current-conveyor CCI . . . . . . . . . . . . . . . . . 49
3.1.1 Linear nonidealities . . . . . . . . . . . . . . . . . . . . . . . 50
3.1.2 Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.1.3 Applications of the CCI . . . . . . . . . . . . . . . . . . . . 53
3.1.4 Push-pull CCI topologies . . . . . . . . . . . . . . . . . . . 54
3.1.5 Low voltage CCI topologies . . . . . . . . . . . . . . . . . . 58
3.2 Second generation current-conveyor CCII . . . . . . . . . . . . . . . 59
3.2.1 Linear nonidealities . . . . . . . . . . . . . . . . . . . . . . . 61
3.2.2 CCII macromodel . . . . . . . . . . . . . . . . . . . . . . . . 63
3.2.3 Applications of the CCII . . . . . . . . . . . . . . . . . . . . 65
3.2.4 Nonlinearity of the class-A CCII . . . . . . . . . . . . . . . . 71
3.2.5 Alternative class-A CCII topologies . . . . . . . . . . . . . . 72
3.2.6 Push-pull CCII topologies . . . . . . . . . . . . . . . . . . . 76
Basic operation of a push-pull CCII+ . . . . . . . . . . . . . 76
Basic operation of a push-pull CCII- . . . . . . . . . . . . . . 78
X-terminal impedance . . . . . . . . . . . . . . . . . . . . . 79
Current gain nonlinearity . . . . . . . . . . . . . . . . . . . . 80
3.3 Third generation current-conveyor CCIII . . . . . . . . . . . . . . . . 84
4 Current-mode feedback amplifiers 89
4.1 Current-feedback operational amplifier . . . . . . . . . . . . . . . . 89
4.1.1 Closed loop bandwidth . . . . . . . . . . . . . . . . . . . . . 91
4.1.2 Integrator implementations . . . . . . . . . . . . . . . . . . . 94
4.1.3 Self-compensation of voltage followers . . . . . . . . . . . . 96
4.1.4 Common-mode rejection . . . . . . . . . . . . . . . . . . . . 97
4.1.5 CMOS implementations . . . . . . . . . . . . . . . . . . . . 99
4.2 Operational floating conveyor . . . . . . . . . . . . . . . . . . . . . 101
4.2.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.2.2 Composite conveyors . . . . . . . . . . . . . . . . . . . . . 103
4.3 Current-mode operational amplifiers . . . . . . . . . . . . . . . . . . 105
4.3.1 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.3.2 Slew rate and full power bandwidth . . . . . . . . . . . . . . 108
4.3.3 Alternative topologies . . . . . . . . . . . . . . . . . . . . . 109
4.4 High-gain current-conveyor . . . . . . . . . . . . . . . . . . . . . . . 111
4.4.1 Linear nonidealities . . . . . . . . . . . . . . . . . . . . . . . 112
4.4.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.4.3 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.4.4 Design example . . . . . . . . . . . . . . . . . . . . . . . . . 119
5 System aspects of current-mode circuits 127
5.1 Input voltage-to-current conversion . . . . . . . . . . . . . . . . . . . 127
5.2 Output current-to-voltage conversion . . . . . . . . . . . . . . . . . . 130
5.3 Differential voltage input structures . . . . . . . . . . . . . . . . . . 133
5.3.1 CMRR enhancement techniques . . . . . . . . . . . . . . . . 134
Common-mode bootstrapping . . . . . . . . . . . . . . . . . 135
Output current subtraction . . . . . . . . . . . . . . . . . . . 135
Composite conveyors . . . . . . . . . . . . . . . . . . . . . . 139
5.4 Differential current input structures . . . . . . . . . . . . . . . . . . . 141
5.5 Single-ended to differential conversion . . . . . . . . . . . . . . . . . 142
5.6 Noise in current-mode circuits . . . . . . . . . . . . . . . . . . . . . 145
5.6.1 Class-A CMOS CCII+ . . . . . . . . . . . . . . . . . . . . . 145
5.6.2 Other low-gain conveyor topologies . . . . . . . . . . . . . . 149
5.6.3 High-gain current-conveyor . . . . . . . . . . . . . . . . . . 149
5.6.4 Other current-mode feedback amplifiers . . . . . . . . . . . . 152
5.6.5 General notes on current amplifier noise . . . . . . . . . . . . 153
6 Current-mode continuous-time filters 157
6.1 Integrator quality factor . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.2 Voltage-mode active-RC integrators . . . . . . . . . . . . . . . . . . 159
6.3 OTA-based integrators . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.1 The effects of process variation and temperature drift . . . . . 162
6.3.2 Transconductance linearity . . . . . . . . . . . . . . . . . . . 164
6.4 Integrators with MOS-resistors . . . . . . . . . . . . . . . . . . . . . 166
6.5 Current-conveyor based filters . . . . . . . . . . . . . . . . . . . . . 167
6.6 Current-mirror based filter . . . . . . . . . . . . . . . . . . . . . . . 171
6.7 High-gain current-conveyor based filters . . . . . . . . . . . . . . . . 176
6.8 Multi-output current integrator with a linearised transconductor . . . . 180
6.8.1 Linearization by drain current difference . . . . . . . . . . . . 181
6.8.2 Linearisation by dynamic biasing . . . . . . . . . . . . . . . 185
6.9 Design case: A 1 MHz current-mode low-pass filter . . . . . . . . . 187
6.9.1 Filter building blocks . . . . . . . . . . . . . . . . . . . . . . 187
The transimpedance driver amplifier . . . . . . . . . . . . . . 188
Multiple-output linearised transconductance element . . . . . 191
Temperature drift compensation of the integrator time constant 191
6.9.2 The first filter realisation . . . . . . . . . . . . . . . . . . . . 194
Integrator Q-enhancement . . . . . . . . . . . . . . . . . . . 196
Experimental results . . . . . . . . . . . . . . . . . . . . . . 199
6.9.3 The second test chip . . . . . . . . . . . . . . . . . . . . . . 202
7 Current-mode logarithmic amplifiers 217
. . . . . . . . . . . . . . . . . . . . . 7.1 Diode-feedback logarithmic amplifiers . . . . . . . . . . . . . . . . 218
7.1.1 Voltage-mode operational amplifier based realizations . . . . 218
7.1.2 Design case: High-gain conveyor based logamp . . . . . . . . 220
BiCMOS implementation of a CCII¥ . . . . . . . . . . . . . 221
Logarithmic peak detector implementation . . . . . . . . . . 221
Post processing of the logarithmic output voltage . . . . . . . 226
Final remarks on the design . . . . . . . . . . . . . . . . . . 233
7.2 Pseudologarithmic amplifiers . . . . . . . . . . . . . . . . . . . . . . 234
7.2.1 Limiting CMOS voltage amplifiers . . . . . . . . . . . . . . 235
7.2.2 Limiting CMOS current amplifiers . . . . . . . . . . . . . . . 237
7.2.3 Accuracy of the pseudologarithmic amplifier . . . . . . . . . 239
7.2.4 Amplitude detection in pseudologarithmic amplifiers . . . . . 240
CMOS rectifiers . . . . . . . . . . . . . . . . . . . . . . . . 240
CMOS squarers . . . . . . . . . . . . . . . . . . . . . . . . . 242
CMOS peak detectors . . . . . . . . . . . . . . . . . . . . . 242
7.2.5 Design case: A 2.5 V CMOS pseudologarithmic current amplifier
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Limiting amplifier . . . . . . . . . . . . . . . . . . . . . . . 247
Current reference . . . . . . . . . . . . . . . . . . . . . . . . 249
Current peak detector . . . . . . . . . . . . . . . . . . . . . . 251
Experimental results . . . . . . . . . . . . . . . . . . . . . . 251
7.3 Other approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Current peak detector with enhanced discharging time constant
adjustment . . . . . . . . . . . . . . . . . . . 256
Conclusions 263

basildy

CMOS Current Amplifiers: Speed versus Nonlinearity

basildy

CMOS Current Amplifiers: Speed versus Nonlinearity

semico_ljj

好贴，有点意思！谢谢！

semico_ljj

Keywords:
analogue integrated circuit, CMOS, current amplifier, current-mode, amplifier
distortion, nonlinearity, continuous-time filter, logarithmic amplifier.

semico_ljj

Preface
Writing this thesis has been a lengthy process. It is difficult to estimate how long
this process exactly was, since the beginning is almost impossible to pinpoint. However,
this event may even be traced back to my first conference presentation in 1991
(ECCTD’91 in Copenhagen), when I first realised that even my research may have
an audience. The writing process was further prolonged because I preferred writing a
book which could additionally be used as a handbook on current-mode analogue integrated
circuit design to writing exclusively a doctoral thesis. I hope that this book
serves at least one of these purposes.
I would like to express my gratitude to my supervisor Professor Kari Halonen for
recruiting me to Electronic Circuit Design Laboratory and introducing to the intriguing
field of analogue integrated circuit design, otherwise I might have ended up doing
something less imaginative. In addition, I would like to thank both Professor Kari
Halonen and Professor Veikko Porra for the various interesting projects and the stateof-
the-art design and measurement facilities in the laboratory, an effort that was not
easy to achieve particularly in the early years of the laboratory, in late 1980’s and early
1990’s.

semico_ljj

Although work is often hard and even unsolvable problems are occasionally encountered,
not a day goes by without laughter at Electronic Circuit Design Laboratory.
For that I owe my gratitude to the entire staff at the laboratory. In addition, during
these almost eleven years at the laboratory I have had numerous colleagues who have
similarly helped me in various other ways. Since this list of acknowledgements would
be extremely long and I would unavoidably miss a name or two, as a compromise,
I must thank You all collectively and name individually here only persons who have
directly contributed to the content of this thesis. Esa Tiiliharju Tero Wahlroos have
helped me in various filter synthesis related problems. Similarly, Marko Kosunen and
Tero Wahlroos have made excellent continuous-time filter implementations using the
filter building blocks described in this thesis. The experience gained in projects with
Harri Kimppa, Harri Riihihuhta, Esa Rantanen, Jarkko Routama and Pasi Ruhanen
has also been valuable in writing this thesis. In addition, I have had numerous fruitful
discussions involving circuit theory and distortion calculations in particular with
Saska Lindfors. These discussion have given my ideas which otherwise would not
have ended up in this thesis. Finally, without several long discussion about effective
and accurate layout design with Jukka Riihiaho, Jukka Wallinheimo, Tero Sillanpää,
Olli Salminen and Kari Halonen, a few desibels worse performance figures may have
resulted in the chips I have designed.
Professors Chris Toumazou and Gordon Roberts are acknowledged for reviewing
my thesis. I would like to express my warmest thanks for their encouraging comments.
The thesis is based on research financed by Technology Development Centre of
Finland, Academy of of Finland, Nokia Networks and Nokia Mobile Phones. In addition,
Foundation for Financial Aid at the Helsinki University and Wihuri Foundation
have given significant support for this work. All of them are gratefully acknowledged.
Kimmo Koli
Espoo,October 2000

semico_ljj

The tradition of implementing analogue circuits by means of voltage amplifiers is almost
as old as the concept of electronic circuit design. The integrated electronic circuit,
however, is a relatively new concept. Furthermore, integrated electronic circuits have
significantly different limitations and strengths to the conventional discrete electronic
circuits have. Since the active devices in integrated circuits amplify current rather than
voltage, various current-mode circuit ideas have emerged after the introduction of the
integrated circuit.
This work deals with analogue integrated circuit design using various types of
current-mode amplifiers. These circuits are analysed and realised using modern CMOS
integration technologies. The dynamic nonlinearities of these circuits are discussed in
detail as in the literature only linear nonidealities and static nonlinearities are conventionally
considered.
The most important open-loop current-mode amplifier is the second-generation
current-conveyor (CCII). For this amplifier, a macromodel is derived that accurately
describes all linear nonidealities. Unlike other reported macromodels, this model can
accurately predict the common-mode behaviour of differential current-conveyor applications.
The accuracy of the model is experimentally verified in the case of currentmode
instrumentational amplifiers. This model is also used to describe the nonidealities
of several other current-mode amplifiers because circuit structures similar to
second-generation current-conveyors are common in such amplifiers.

pzhangosu

好书，感谢分享。

一意孤行

上帝爱你！