ICC基础

tutu1992

icc_shell> create_mw_lib  -technology /home/tusq/ICC_lab/IC_Compiler_2010.12-SP2/ref/tech/cb13_6m.tf -mw_reference_library {/home/tusq/ICC_lab/icc_test1/ref/mw_lib/sc /home/tusq/ICC_lab/icc_test1/ref/mw_lib/io /home/tusq/ICC_lab/icc_test1/ref/mw_lib/ram16x128} -bus_naming_style {[%d]}  -open  /home/tusq/ICC_lab/IC_Compiler_2010.12-SP2/lab1_data_setup/$my_mw_lib
Start to load technology file /home/tusq/ICC_lab/IC_Compiler_2010.12-SP2/ref/tech/cb13_6m.tf.
Warning: Layer 'PRODUM' is missing the attribute 'minSpacing'. (line 312) (TFCHK-014)
Warning: Layer 'PRODUM' is missing the attribute 'minWidth'. (line 312) (TFCHK-014)
Warning: CapModel sections are missing. Capacitance models should be loaded with a TLU+ file later. (TFCHK-084)
Technology file /home/tusq/ICC_lab/IC_Compiler_2010.12-SP2/ref/tech/cb13_6m.tf has been loaded successfully.
{risc_chip.mw}
icc_shell> import_designs -format verilog -top RISC_CHIP -cel RISC_CHIP {/home/tusq/ICC_lab/IC_Compiler_2010.12-SP2/lab1_data_setup/design_data/RISC_CHIP.v}
Loading db file '/home/tusq/ICC_lab/icc_test1/ref/db/sc_max.db'
Loading db file '/home/tusq/ICC_lab/icc_test1/ref/db/io_max.db'
Loading db file '/home/tusq/ICC_lab/icc_test1/ref/db/ram16x128_max.db'
Loading db file '/eda/synopsys/icc_vL-2016.03-SP1/libraries/syn/gtech.db'
Loading db file '/eda/synopsys/icc_vL-2016.03-SP1/libraries/syn/standard.sldb'

*****  Verilog HDL translation! *****

*****    Start Pass 1 *****
Compiling source file /home/tusq/ICC_lab/IC_Compiler_2010.12-SP2/lab1_data_setup/design_data/RISC_CHIP.v

*****  Pass 1 Complete *****
Elapsed =    0:00:00, CPU =    0:00:00

*****  Verilog HDL translation! *****

*****    Start Pass 2 *****
Compiling source file /home/tusq/ICC_lab/IC_Compiler_2010.12-SP2/lab1_data_setup/design_data/RISC_CHIP.v
Error:   /home/tusq/ICC_lab/IC_Compiler_2010.12-SP2/lab1_data_setup/design_data/RISC_CHIP.v:12:  module ad01d0 is not defined.
(VER-500)
Error: Module 'ad01d0' is not defined.  (MWNL-297)
Error:   /home/tusq/ICC_lab/IC_Compiler_2010.12-SP2/lab1_data_setup/design_data/RISC_CHIP.v:12: ERROR: near line 12: Port connection failed.
(VER-500)

Error: Verilog parser cannot parse the /home/tusq/ICC_lab/IC_Compiler_2010.12-SP2/lab1_data_setup/design_data/RISC_CHIP.v source file. (MWNL-047)
Error: Current design is not defined. (UID-4)
0
每一步都是按guide做的，为什么老是有这个错误，反复多次都是这样？求助会的大佬帮忙。。。多谢了

keenkeen

ad01d0这个module有问题啊