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发表于 2009-3-19 16:37:18
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I am thinking you are talking about IC layout issue, in which i have done before:
the drawn layer is the layer like donut, rectangle, etc. you draw by using EDA software, such as L-edit, virtuoso,etc.
while the generated layer is got by some kind of logic calculation, such as : a or b means a+b,etc.
hope it can help you... |
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