大家帮忙看看这个vhdl的乘法器程序！

tulipbeyond

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
entity const_mult is
generic(N:integer:=8;
   M:integer:=8;

cst_mult:integer:=66);
port
(clock:in std_logic;
clockenable:in std_logic;
reset:in std_logic;
color:in std_logic_vector(n-1 downto 0);
color_out: out std_logic_vector(m+n-1 downto 0)
);
end const_mult;
architecture rtl of const_mult is
begin
color_kcm:process(clock,reset)
begin
if (reset= '0' ) then
color_out<=(others=> '0');
elsif (clock'event and clock='1')then
if (clockenable= '1')then
color_out<=conv_std_logic_vector(conv_unsigned(cst_mult,M)*unsigned(color),out_size);
end if;
end if;

end process;
end rtl;




好像不太对，哪位能帮我找找错误，谢谢大家了！