新手求助各位前辈，Astro跑后端时如何消除hold time violation

xiaoming233 · 发表于 2018-3-27 10:25:53

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本帖最后由 xiaoming233 于 2018-3-27 12:23 编辑

各位前辈，我是新人，第一次做后端的工作，现在布局布线用的工具是Astro，工艺是SMIC 180nm的工艺，时钟很慢是1MHz。
跑Astro是用的师兄以前的脚本，在上面做一些改动来跑的。可能对后端的一些内容理解的比较不透彻，修改的参数会有些问题，现在跑出来的时序，setup time是通过的，但是hold time violation一直存在，想请问前辈们，我该怎么调参数来修hold time呢？

优化设置是这样的，时钟周期是1000
优化设置.PNG

这是时序报告，请大家帮我看看问题该怎么解决，谢谢大家

*********************************************************************************
*
* Astro Timing Report
*
* Tool : Astro
* Version : Z-2007.03-SP12 for IA.32 -- Nov_13,_2009
* Design  : top
* Date : Thu Mar 22 14:17:17 2018
*
*********************************************************************************
*
*********************************************************************************
*
* Design Setup
*
* Analysis Type                : Max Min
* Parasitic Source             : from LPE
* LPE Operating Cond          : Max Min
* LPE Mode                      : Real_RC
* Wire Delay                   : Medium Effort
* Time Borrowing                : Enabled
* Time Borrowing Method       : Standard
* Preset/Clear Arcs             : Disabled
* Recovery/Removal Arcs       : Enabled
* Scan Enable                   : Enabled
* Inter Clock Paths             : Enabled
* Default Clock                : Enabled
* Ideal Network Delay          : Disabled
* Mixed Clock/Signal Paths    : Enabled
* Include Xtalk Induced Delay : Disabled
* Include Non-Propagated Nets : Disabled
* Include Lib Max Transition    : Enabled
* Include Lib Max Capacitance : Enabled
* Ignore Clock Uncertainty    : Enabled
* Ignore Propagated Clock       : Disabled
* Set IO Clock Latency          : Disabled
* Enable Data Check             : Enabled
* Load Useful Skew From DB    : Disabled
* Enable Clock Gating Checks    : Enabled
* Multiple Clocks Per Register : Enabled
* Include CRPR                : Disabled
*
*********************************************************************************
*
*********************************************************************************
*
* Reasons For No Optimization
*
* NDT : Don't touch net.
* IDT : Don't touch instance.
* FIX : Fixed instance.
* MDR : Multi-Driven net.
* PCP : Huge pin cap on the net.
* TRI : Tristate net.
* PRE : Preserve Logic.
* DIS : Disabled edges on the net.
* NEQ : No equivalent cells.
*
*********************************************************************************

**************************************************************************
*
*          Slack Histogram
*
**************************************************************************
               Setup             Hold
   Slack Incr. Accu.    Incr. Accu.
--------------------------------------------------------------------------
-99.00    0       0       2       2
-98.00    0       0       0       2
-97.00    0       0       0       2
-96.00    0       0       0       2
-95.00    0       0       0       2
-94.00    0       0       0       2
-93.00    0       0       0       2
-92.00    0       0       0       2
-91.00    0       0       0       2
-90.00    0       0       0       2
-89.00    0       0       0       2
-88.00    0       0       0       2
-87.00    0       0       0       2
-86.00    0       0       0       2
-85.00    0       0       0       2
-84.00    0       0       0       2
-83.00    0       0       0       2
-82.00    0       0       0       2
-81.00    0       0       0       2
-80.00    0       0       0       2
-79.00    0       0       0       2
-78.00    0       0       0       2
-77.00    0       0       0       2
-76.00    0       0       0       2
-75.00    0       0       0       2
-74.00    0       0       0       2
-73.00    0       0       0       2
-72.00    0       0       0       2
-71.00    0       0       0       2
-70.00    0       0       0       2
-69.00    0       0       0       2
-68.00    0       0       0       2
-67.00    0       0       0       2
-66.00    0       0       0       2
-65.00    0       0       0       2
-64.00    0       0       0       2
-63.00    0       0       0       2
-62.00    0       0       0       2
-61.00    0       0       0       2
-60.00    0       0       0       2
-59.00    0       0       0       2
-58.00    0       0       0       2
-57.00    0       0       0       2
-56.00    0       0       0       2
-55.00    0       0       0       2
-54.00    0       0       0       2
-53.00    0       0       0       2
-52.00    0       0       0       2
-51.00    0       0       0       2
-50.00    0       0       0       2
-49.00    0       0    237    239
-48.00    0       0       12    251
-47.00    0       0       0    251
-46.00    0       0       0    251
-45.00    0       0       0    251
-44.00    0       0       0    251
-43.00    0       0       0    251
-42.00    0       0       0    251
-41.00    0       0       0    251
-40.00    0       0       0    251
-39.00    0       0       0    251
-38.00    0       0       0    251
-37.00    0       0       0    251
-36.00    0       0       0    251
-35.00    0       0       0    251
-34.00    0       0       0    251
-33.00    0       0       0    251
-32.00    0       0       0    251
-31.00    0       0       0    251
-30.00    0       0       0    251
-29.00    0       0       0    251
-28.00    0       0       0    251
-27.00    0       0       0    251
-26.00    0       0       0    251
-25.00    0       0       0    251
-24.00    0       0       0    251
-23.00    0       0       0    251
-22.00    0       0       0    251
-21.00    0       0       0    251
-20.00    0       0       0    251
-19.00    0       0       0    251
-18.00    0       0       0    251
-17.00    0       0       0    251
-16.00    0       0       0    251
-15.00    0       0       0    251
-14.00    0       0       0    251
-13.00    0       0       0    251
-12.00    0       0       0    251
-11.00    0       0       0    251
-10.00    0       0       0    251
   -9.00    0       0       0    251
   -8.00    0       0       0    251
   -7.00    0       0       0    251
   -6.00    0       0       0    251
   -5.00    0       0       0    251
   -4.00    0       0       0    251
   -3.00    0       0       0    251
   -2.00    0       0       0    251
   -1.00    0       0       0    251
   0.00    0       0       0    251
   8.00    0       0    145    396
   16.00    0       0       0    396
   24.00    0       0       0    396
   32.00    0       0       0    396
   40.00    0       0       0    396
   48.00    0       0       0    396
   56.00    0       0       0    396
   64.00    0       0       0    396
   72.00    0       0       0    396
   80.00    0       0       0    396
   88.00    0       0       0    396
   96.00    0       0       0    396
104.00    0       0       0    396
112.00    0       0       0    396
120.00    0       0       0    396
128.00    0       0       0    396
136.00    0       0       0    396
144.00    0       0       0    396
152.00    0       0       0    396
160.00    0       0       0    396
168.00    0       0       0    396
176.00    0       0       0    396
184.00    0       0       0    396
192.00    0       0       0    396
200.00    0       0       0    396
208.00    0       0       0    396
216.00    0       0       0    396
224.00    0       0       0    396
232.00    0       0       0    396
240.00    0       0       0    396
248.00    0       0       0    396
256.00    0       0       0    396
264.00    0       0       0    396
272.00    0       0       0    396
280.00    0       0       0    396
288.00    0       0       0    396
296.00    0       0       0    396
304.00    0       0       0    396
312.00    0       0       0    396
320.00    0       0       0    396
328.00    0       0       0    396
336.00    0       0       0    396
344.00    0       0       0    396
352.00    0       0       0    396
360.00    0       0       0    396
368.00    0       0       0    396
376.00    0       0       0    396
384.00    0       0       0    396
392.00    0       0       0    396
400.00    2       2       0    396
408.00    0       2       0    396
416.00    0       2       0    396
424.00    0       2       0    396
432.00    0       2       0    396
440.00    0       2       0    396
448.00    0       2       0    396
456.00    0       2       1    397
464.00    0       2       0    397
472.00    0       2       0    397
480.00    0       2       0    397
488.00    0       2       0    397
496.00    37    39       0    397
504.00    86    125       2    399
512.00    0    125       0    399
520.00    0    125       0    399
528.00    0    125       0    399
536.00    0    125       0    399
544.00    0    125       0    399
552.00    0    125       0    399
560.00    0    125       0    399
568.00    0    125       0    399
576.00    0    125       0    399
584.00    0    125       0    399
592.00    0    125       0    399
600.00    0    125       0    399
608.00    0    125       0    399
616.00    0    125       0    399
624.00    0    125       0    399
632.00    0    125       0    399
640.00    0    125       0    399
648.00    0    125       0    399
656.00    0    125       0    399
664.00    0    125       0    399
672.00    0    125       0    399
680.00    0    125       0    399
688.00    0    125       0    399
696.00    0    125       0    399
704.00    0    125       0    399
712.00    0    125       0    399
720.00    0    125       0    399
728.00    0    125       0    399
736.00    0    125       0    399
744.00    0    125       0    399
752.00    0    125       0    399
760.00    0    125       0    399
768.00    0    125       0    399
776.00    0    125       0    399
784.00    0    125       0    399
792.00    0    125       0    399
800.00    1    126       0    399
808.00    0    126       0    399
816.00    0    126       0    399
824.00    0    126       0    399
832.00    0    126       0    399
840.00    0    126       0    399
848.00    0    126       0    399
856.00    0    126       0    399
864.00    0    126       0    399
872.00    0    126       0    399
880.00    0    126       0    399
888.00    0    126       0    399
896.00    3    129       0    399
904.00 155    284       0    399
912.00    0    284       0    399
920.00    0    284       0    399
928.00    0    284       0    399
936.00    0    284       0    399
944.00    0    284       0    399
952.00    0    284       0    399
960.00    0    284       0    399
968.00    0    284       0    399
976.00    0    284       0    399
984.00    0    284       0    399
992.00    0    284       0    399
1000.00 115    399       0    399

*********************************************************************************
*
* Start point : u_spi/reg_done2_reg/CKN
* ( Falling edge-triggered flipflop clocked by I_sclk )
*
* End point : u_spi/IRRreg_reg_22_/RN
* ( Rising edge-triggered flipflop clocked by I_sclk at CK )
*
* Clock Group : ASYNC_GROUP
* Delay Type  : Max
* Slack    : 497.5348  (MET)
*
*********************************************************************************

Port/Pin          Cap Fanout    Trans.    Incr    Arri Reason  Master/Net
---------------------------------------------------------------------------------
Falling edge of clock I_sclk                500.0000 500.0000
Clock Source delay                            0.0000 500.0000
Clock Network delay                         100.0000 600.0000
---------------------------------------------------------------------------------
u_spi/reg_done2_reg/CKN
                                    0.0000    0.0000 600.0000 f       FFDNRHDLX
u_spi/reg_done2_reg/QN
                  0.0081    1    0.2085    0.3876 600.3876 f       u_spi/n360
u_spi/U22/B                         0.2088    0.0004 600.3880 f       AOI211HD1X
u_spi/U22/Z       0.0398    3    1.0522    0.5695 600.9575 r       u_spi/n409
u_spi/U22ASTttcInst179/A
                                    1.0606    0.0105 600.9680 r       BUFHD2X
u_spi/U22ASTttcInst179/Z
                  0.0144    2    0.1471    0.2407 601.2087 r       u_spi/n409ASTttcNet180
u_spi/U22ASThfnInst14/A
                                    0.1478    0.0009 601.2096 r       BUFCLKHD2X
u_spi/U22ASThfnInst14/Z
                  0.0443    6    0.2633    0.2147 601.4243 r       u_spi/n409ASThfnNet14
u_spi/U22ASTttcInst522/A
                                    0.2650    0.0021 601.4265 r       BUFCLKHD2X
u_spi/U22ASTttcInst522/Z
                  0.0173    2    0.1444    0.1627 601.5892 r       u_spi/n409ASTttcNet455
u_spi/U22ASTttcInst538/A
                                    0.1449    0.0006 601.5897 r       BUFHD2X
u_spi/U22ASTttcInst538/Z
                  0.0296    5    0.1969    0.1829 601.7726 r       u_spi/n409ASTttcNet460
u_spi/U22ASTttcInst129/A
                                    0.1983    0.0018 601.7744 r       BUFCLKHD2X
u_spi/U22ASTttcInst129/Z
                  0.0159    2    0.1360    0.1487 601.9232 r       u_spi/n409ASTttcNet130
u_spi/U22ASTttcInst551/A
                                    0.1368    0.0010 601.9241 r       BUFHD1X
u_spi/U22ASTttcInst551/Z
                  0.0259    4    0.3058    0.2243 602.1484 r       u_spi/n409ASTttcNet473
u_spi/IRRreg_reg_22_/RN
                                    0.3075    0.0021 602.1505 r       FFDRHDLX

---------------------------------------------------------------------------------

Rising edge of clock I_sclk                1000.0000  1000.0000
Clock Source delay                            0.0000  1000.0000
Clock Network delay                         100.0000  1100.0000
Clock Skew                                     0.0000  1100.0000
Recovery time                                  0.3147  1099.6853
---------------------------------------------------------------------------------
Required time                                           1099.6853
Arrival time                                           602.1505
---------------------------------------------------------------------------------
Slack                                                    497.5348  (MET)

*********************************************************************************
*
* Start point : u_spi/RdStb_reg/CKN
* ( Falling edge-triggered flipflop clocked by I_sclk )
*
* End point : u_spi/IRRreg_reg_20_/D
* ( Rising edge-triggered flipflop clocked by I_sclk at CK )
*
* Clock Group : I_sclk
* Delay Type  : Max
* Slack    : 494.6034  (MET)
*
*********************************************************************************

Port/Pin          Cap Fanout    Trans.    Incr    Arri Reason  Master/Net
---------------------------------------------------------------------------------
Falling edge of clock I_sclk                500.0000 500.0000
Clock Source delay                            0.0000 500.0000
Clock Network delay                         100.0000 600.0000
---------------------------------------------------------------------------------
u_spi/RdStb_reg/CKN
                                    0.0000    0.0000 600.0000 f       FFDNRHDLX
u_spi/RdStb_reg/QN
                  0.0325    3    0.4514    0.5550 600.5551 f       u_spi/n400
u_spi/U703/AN                      0.4561    0.0058 600.5609 f       NAND4B1HDLX
u_spi/U703/Z       0.0225    1    0.7200    0.5157 601.0765 f       u_spi/n298
u_spi/U693/C                         0.7219    0.0024 601.0790 f       NOR4HD1X
u_spi/U693/Z       0.0218    2    0.9362    0.5426 601.6215 r       u_spi/n969ASTHNet26
u_spi/U693ASThfnInst26/A
                                    0.9369    0.0008 601.6223 r       BUFCLKHD2X
u_spi/U693ASThfnInst26/Z
                  0.0263    3    0.1955    0.2609 601.8832 r       u_spi/n969ASThfnNet27
u_spi/U693ASTttcInst103/A
                                    0.1960    0.0006 601.8838 r       BUFHD2X
u_spi/U693ASTttcInst103/Z
                  0.0580    7    0.3329    0.2607 602.1445 r       u_spi/n969ASTttcNet104
u_spi/U532/A                         0.3352    0.0029 602.1473 r       AND2HD1X
u_spi/U532/Z       0.0133    2    0.2152    0.2296 602.3769 r       u_spi/n294
u_spi/U531/B                         0.2161    0.0011 602.3781 r       NOR3HDLX
u_spi/U531/Z       0.0076    1    0.3466    0.1259 602.5040 f       u_spi/n295
u_spi/U530/AN                      0.3469    0.0003 602.5043 f       AOI21B2HDLX
u_spi/U530/Z       0.0213    2    0.3441    0.3662 602.8705 f       u_spi/n292
u_spi/U345/A                         0.3450    0.0011 602.8716 f       NAND2HDLX
u_spi/U345/Z       0.0221    2    0.5406    0.3368 603.2084 r       u_spi/n667
u_spi/U226/A                         0.5411    0.0005 603.2089 r       INVCLKHD4X
u_spi/U226/Z       0.0477    6    0.2307    0.1676 603.3765 f       u_spi/n533
u_spi/U226ASTttcInst217/A
                                    0.2322    0.0019 603.3784 f       BUFCLKHD2X
u_spi/U226ASTttcInst217/Z
                  0.0405    6    0.2118    0.2384 603.6168 f       u_spi/n533ASTttcNet218
u_spi/U226ASTttcInst216/A
                                    0.2121    0.0003 603.6171 f       BUFCLKHD2X
u_spi/U226ASTttcInst216/Z
                  0.0110    2    0.1018    0.1572 603.7743 f       u_spi/n533ASTttcNet217
u_spi/U226ASTttcInst505/A
                                    0.1018    0.0000 603.7743 f       BUFHD2X
u_spi/U226ASTttcInst505/Z
                  0.0333    5    0.1500    0.1972 603.9716 f       u_spi/n533ASTttcNet438
u_spi/U226ASTttcInst215/A
                                    0.1525    0.0031 603.9746 f       BUFCLKHD2X
u_spi/U226ASTttcInst215/Z
                  0.0430    6    0.2202    0.2277 604.2023 f       u_spi/n533ASTttcNet216
u_spi/U226ASTttcInst214/A
                                    0.2225    0.0029 604.2052 f       BUFHD2X
u_spi/U226ASTttcInst214/Z
                  0.0352    6    0.1584    0.2296 604.4348 f       u_spi/n533ASTttcNet215
u_spi/U701/B                         0.1593    0.0011 604.4359 f       AOI221HDLX
u_spi/U701/Z       0.0108    1    0.6707    0.4171 604.8530 r       u_spi/n235
u_spi/U718/A                         0.6714    0.0008 604.8538 r       INVHDPX
u_spi/U718/Z       0.0058    1    0.1432    0.0665 604.9203 f       u_spi/n931
u_spi/U716/A                         0.1434    0.0003 604.9206 f       AOI21HDLX
u_spi/U716/Z       0.0072    1    0.3539    0.2311 605.1517 r       u_spi/n232
u_spi/U715/A                         0.3543    0.0004 605.1521 r       INVHDPX
u_spi/U715/Z       0.0043    1    0.0912    0.0468 605.1989 f       u_spi/n930
u_spi/IRRreg_reg_20_/D
                                    0.0912    0.0001 605.1990 f       FFDRHDLX

---------------------------------------------------------------------------------

Rising edge of clock I_sclk                1000.0000  1000.0000
Clock Source delay                            0.0000  1000.0000
Clock Network delay                         100.0000  1100.0000
Clock Skew                                     0.0000  1100.0000
Setup time                                     0.1976  1099.8024
---------------------------------------------------------------------------------
Required time                                           1099.8024
Arrival time                                           605.1990
---------------------------------------------------------------------------------
Slack                                                    494.6034  (MET)

*********************************************************************************
*
* Start point : u_spi/RdStb_reg/CKN
* ( Falling edge-triggered flipflop clocked by I_sclk )
*
* End point : O_sdo_en
* ( Output port clocked by I_sclk )
*
* Clock Group : OUTPUTS
* Delay Type  : Max
* Slack    : 398.6363  (MET)
*
*********************************************************************************

Port/Pin          Cap Fanout    Trans.    Incr    Arri Reason  Master/Net
---------------------------------------------------------------------------------
Falling edge of clock I_sclk                500.0000 500.0000
Clock Source delay                            0.0000 500.0000
Clock Network delay                         100.0000 600.0000
---------------------------------------------------------------------------------
u_spi/RdStb_reg/CKN
                                    0.0000    0.0000 600.0000 f       FFDNRHDLX
u_spi/RdStb_reg/QN
                  0.0325    3    0.4514    0.5550 600.5551 f       u_spi/n400
u_spi/U692/B                         0.4557    0.0053 600.5604 f       NOR3HDLX
u_spi/U692/Z       0.0143    1    0.7365    0.4351 600.9955 r       n265
U145/A                               0.7375    0.0012 600.9967 r       BUFCLKHD2X
U145/Z             0.0721    1    0.4091    0.3592 601.3558 r PCP  O_sdo_en
O_sdo_en                            0.4154    0.0078 601.3636 r

---------------------------------------------------------------------------------

Rising edge of clock I_sclk                1000.0000  1000.0000
Clock Source delay                            0.0000  1000.0000
Clock Network delay                         100.0000  1100.0000
Clock Skew                                     0.0000  1100.0000
Output delay                                  100.0000  1000.0000
---------------------------------------------------------------------------------
Required time                                           1000.0000
Arrival time                                           601.3637
---------------------------------------------------------------------------------
Slack                                                    398.6363  (MET)

*********************************************************************************
*
* Start point : I_csb
* ( Input port clocked by I_sclk )
*
* End point : u_spi/BITcnt_reg_4_/D
* ( Rising edge-triggered flipflop clocked by I_sclk at CK )
*
* Clock Group : INPUTS
* Delay Type  : Max
* Slack    : 895.6903  (MET)
*
*********************************************************************************

Port/Pin          Cap Fanout    Trans.    Incr    Arri Reason  Master/Net
---------------------------------------------------------------------------------
Rising edge of clock I_sclk                   0.0000    0.0000
Clock Source delay                            0.0000    0.0000
Clock Network delay                         100.0000 100.0000
Input delay                                  100.0000 200.0000
---------------------------------------------------------------------------------
I_csb             0.0319    1    0.1359    0.0412 200.0412 r       I_csb
U152/A                               0.1383    0.0030 200.0441 r       BUFCLKHD2X
U152/Z             0.0466    2    0.2746    0.2186 200.2627 r       n143
u_spi/U152ASThfnInst22/A
                                    0.2762    0.0020 200.2648 r       BUFCLKHD2X
u_spi/U152ASThfnInst22/Z
                  0.0527    7    0.3074    0.2551 200.5198 r       u_spi/n143ASThfnNet22
u_spi/U152ASTttcInst109/A
                                    0.3097    0.0028 200.5226 r       BUFHD2X
u_spi/U152ASTttcInst109/Z
                  0.0425    6    0.2588    0.2432 200.7658 r       u_spi/n143ASTttcNet110
u_spi/U152ASTttcInst108/A
                                    0.2617    0.0036 200.7695 r       BUFHD1X
u_spi/U152ASTttcInst108/Z
                  0.0442    4    0.4889    0.3278 201.0972 r       u_spi/n143ASTttcNet109
u_spi/U152ASTttcInst107/A
                                    0.4913    0.0030 201.1003 r       BUFCLKHD2X
u_spi/U152ASTttcInst107/Z
                  0.0081    2    0.1116    0.1715 201.2718 r       u_spi/n143ASTttcNet108
u_spi/U152ASTttcInst552/A
                                    0.1119    0.0003 201.2721 r       BUFHD2X
u_spi/U152ASTttcInst552/Z
                  0.0501    4    0.2923    0.2285 201.5006 r       u_spi/n143ASTttcNet474
u_spi/U341/A                         0.2955    0.0040 201.5046 r       INVCLKHD2X
u_spi/U341/Z       0.0345    4    0.2431    0.1679 201.6724 f       u_spi/n639
u_spi/U341ASTttcInst191/A
                                    0.2463    0.0040 201.6765 f       BUFHD2X
u_spi/U341ASTttcInst191/Z
                  0.0388    4    0.1683    0.2433 201.9198 f       u_spi/n639ASTttcNet192
u_spi/U341ASTttcInst189/A
                                    0.1693    0.0014 201.9212 f       BUFHD2X
u_spi/U341ASTttcInst189/Z
                  0.0606    5    0.2251    0.2588 202.1799 f       u_spi/n639ASTttcNet190
u_spi/U16/B                         0.2265    0.0018 202.1818 f       AND2HD1X
u_spi/U16/Z       0.0217    2    0.1892    0.2537 202.4355 f       u_spi/n20
u_spi/U91/A                         0.1905    0.0016 202.4370 f       INVHDLX
u_spi/U91/Z       0.0487    2    0.9951    0.5185 202.9555 r       u_spi/n170
u_spi/U469/A                         1.0007    0.0069 202.9624 r       INVHDLX
u_spi/U469/Z       0.0323    2    0.5581    0.3800 203.3424 f       u_spi/n937
u_spi/U546/B                         0.5617    0.0045 203.3469 f       OAI22HDLX
u_spi/U546/Z       0.0212    1    0.9400    0.5558 203.9028 r       u_spi/n438
u_spi/BITcnt_reg_4_/D
                                    0.9414    0.0017 203.9045 r       FFDRHDLX

---------------------------------------------------------------------------------

Rising edge of clock I_sclk                1000.0000  1000.0000
Clock Source delay                            0.0000  1000.0000
Clock Network delay                         100.0000  1100.0000
Clock Skew                                     0.0000  1100.0000
Setup time                                     0.4052  1099.5948
---------------------------------------------------------------------------------
Required time                                           1099.5948
Arrival time                                           203.9045
---------------------------------------------------------------------------------
Slack                                                    895.6903  (MET)

*********************************************************************************
*
* Start point : I_csb
* ( Input port clocked by I_sclk )
*
* End point : u_spi/IRReg_hold_flag_reg/RN
* ( Rising edge-triggered flipflop clocked by I_sclk at CK )
*
* Clock Group : ASYNC_GROUP
* Delay Type  : Min
* Slack    : -49.3162  (VIOLATED)
*
*********************************************************************************

Port/Pin          Cap Fanout    Trans.    Incr    Arri Reason  Master/Net
---------------------------------------------------------------------------------
Rising edge of clock I_sclk                   0.0000    0.0000
Clock Source delay                            0.0000    0.0000
Clock Network delay                         100.0000 100.0000
Input delay                                  -50.0000 50.0000
---------------------------------------------------------------------------------
I_csb             0.0306    1    0.0500    0.0161 50.0161 f       I_csb
U152/A                               0.0510    0.0013 50.0174 f       BUFCLKHD2X
U152/Z             0.0449    2    0.1150    0.1052 50.1226 f       n143
u_spi/U152ASThfnInst22/A
                                    0.1154    0.0006 50.1231 f       BUFCLKHD2X
u_spi/U152ASThfnInst22/Z
                  0.0524    7    0.1334    0.1239 50.2470 f       u_spi/n143ASThfnNet22
u_spi/U152ASTttcInst109/A
                                    0.1342    0.0009 50.2480 f       BUFHD2X
u_spi/U152ASTttcInst109/Z
                  0.0425    6    0.0915    0.1165 50.3645 f       u_spi/n143ASTttcNet110
u_spi/U22/D                         0.0918    0.0004 50.3649 f       AOI211HD1X
u_spi/U22/Z       0.0388    3    0.4289    0.2103 50.5752 r       u_spi/n409
u_spi/U22ASThfnInst16/A
                                    0.4296    0.0008 50.5761 r       BUFCLKHD2X
u_spi/U22ASThfnInst16/Z
                  0.0269    4    0.1059    0.1015 50.6775 r       u_spi/n409ASThfnNet16
u_spi/IRReg_hold_flag_reg/RN
                                    0.1067    0.0011 50.6786 r       FFDRHDLX

---------------------------------------------------------------------------------

Rising edge of clock I_sclk                   0.0000    0.0000
Clock Source delay                            0.0000    0.0000
Clock Network delay                         100.0000 100.0000
Clock Skew                                     0.0000 100.0000
Removal time                                  -0.0052 99.9948
---------------------------------------------------------------------------------
Required time                                           99.9948
Arrival time                                              50.6786
---------------------------------------------------------------------------------
Slack                                                    -49.3162  (VIOLATED)

*********************************************************************************
*
* Start point : u_myfifo/r1_wptr_reg_0_/CK
* ( Rising edge-triggered flipflop clocked by I_sclk )
*
* End point : u_myfifo/r2_wptr_reg_0_/D
* ( Rising edge-triggered flipflop clocked by I_sclk at CK )
*
* Clock Group : I_sclk
* Delay Type  : Min
* Slack    : 0.2059  (MET)
*
*********************************************************************************

Port/Pin          Cap Fanout    Trans.    Incr    Arri Reason  Master/Net
---------------------------------------------------------------------------------
Rising edge of clock I_sclk                   0.0000    0.0000
Clock Source delay                            0.0000    0.0000
Clock Network delay                         100.0000 100.0000
---------------------------------------------------------------------------------
u_myfifo/r1_wptr_reg_0_/CK
                                    0.0000    0.0000 100.0000 r       FFDRHDLX
u_myfifo/r1_wptr_reg_0_/Q
                  0.0041    1    0.0495    0.2018 100.2018 f       u_myfifo/r1_wptr[0]
u_myfifo/r2_wptr_reg_0_/D
                                    0.0496    0.0001 100.2019 f       FFDRHDLX

---------------------------------------------------------------------------------

Rising edge of clock I_sclk                   0.0000    0.0000
Clock Source delay                            0.0000    0.0000
Clock Network delay                         100.0000 100.0000
Clock Skew                                     0.0000 100.0000
Hold time                                     -0.0041 99.9959
---------------------------------------------------------------------------------
Required time                                           99.9959
Arrival time                                           100.2019
---------------------------------------------------------------------------------
Slack                                                    0.2059  (MET)

*********************************************************************************
*
* Start point : I_csb
* ( Input port clocked by I_sclk )
*
* End point : O_sdo_en
* ( Output port clocked by I_sclk )
*
* Clock Group : OUTPUTS
* Delay Type  : Min
* Slack    : -99.5471  (VIOLATED)
*
*********************************************************************************

Port/Pin          Cap Fanout    Trans.    Incr    Arri Reason  Master/Net
---------------------------------------------------------------------------------
Rising edge of clock I_sclk                   0.0000    0.0000
Clock Source delay                            0.0000    0.0000
Clock Network delay                         100.0000 100.0000
Input delay                                  -50.0000 50.0000
---------------------------------------------------------------------------------
I_csb             0.0306    1    0.0598    0.0175 50.0175 r       I_csb
U152/A                               0.0608    0.0013 50.0187 r       BUFCLKHD2X
U152/Z             0.0449    2    0.1340    0.1011 50.1199 r       n143
u_spi/U152ASThfnInst22/A
                                    0.1345    0.0006 50.1204 r       BUFCLKHD2X
u_spi/U152ASThfnInst22/Z
                  0.0524    7    0.1557    0.1154 50.2358 r       u_spi/n143ASThfnNet22
u_spi/U692/C                         0.1561    0.0005 50.2363 r       NOR3HDLX
u_spi/U692/Z       0.0140    1    0.1158    0.0678 50.3042 f       n265
U145/A                               0.1162    0.0004 50.3046 f       BUFCLKHD2X
U145/Z             0.0716    1    0.1706    0.1453 50.4499 f PCP  O_sdo_en
O_sdo_en                            0.1730    0.0030 50.4529 f

---------------------------------------------------------------------------------

Rising edge of clock I_sclk                   0.0000    0.0000
Clock Source delay                            0.0000    0.0000
Clock Network delay                         100.0000 100.0000
Clock Skew                                     0.0000 100.0000
Output delay                                  50.0000 150.0000
---------------------------------------------------------------------------------
Required time                                           150.0000
Arrival time                                              50.4529
---------------------------------------------------------------------------------
Slack                                                    -99.5471  (VIOLATED)

*********************************************************************************
*
* Start point : I_sdi
* ( Input port clocked by I_sclk )
*
* End point : u_spi/SerBits_reg_1_/D
* ( Rising edge-triggered flipflop clocked by I_sclk at CK )
*
* Clock Group : INPUTS
* Delay Type  : Min
* Slack    : -49.7450  (VIOLATED)
*
*********************************************************************************

Port/Pin          Cap Fanout    Trans.    Incr    Arri Reason  Master/Net
---------------------------------------------------------------------------------
Rising edge of clock I_sclk                   0.0000    0.0000
Clock Source delay                            0.0000    0.0000
Clock Network delay                         100.0000 100.0000
Input delay                                  -50.0000 50.0000
---------------------------------------------------------------------------------
I_sdi             0.0509    2    0.0641    0.0268 50.0268 f       I_sdi
u_spi/U840/C                         0.0663    0.0027 50.0295 f       NAND3HDLX
u_spi/U840/Z       0.0207    3    0.2318    0.1212 50.1507 r       u_spi/n103
u_spi/U876/A                         0.2321    0.0004 50.1512 r       OAI21HDLX
u_spi/U876/Z       0.0162    1    0.1268    0.0888 50.2400 f       u_spi/n436
u_spi/SerBits_reg_1_/D
                                    0.1273    0.0006 50.2406 f       FFDRHDLX

---------------------------------------------------------------------------------

Rising edge of clock I_sclk                   0.0000    0.0000
Clock Source delay                            0.0000    0.0000
Clock Network delay                         100.0000 100.0000
Clock Skew                                     0.0000 100.0000
Hold time                                     -0.0144 99.9856
---------------------------------------------------------------------------------
Required time                                           99.9856
Arrival time                                              50.2406
---------------------------------------------------------------------------------
Slack                                                    -49.7450  (VIOLATED)

Timing Report summary

Paths reported = 8
Violations    = 3
---------------------------------------------------------------------------------

*********************************************************************************
*
*
*  Transition Time Violations
*
*
*  Constraint Types:
*  S -> SDC constraint
*  C -> CLF/lib constraint
*  G -> Astro Global constraint
*
*********************************************************************************

Cell Trans Constraint  MasterCell             Reason    Cell/Port Name
---------------------------------------------------------------------------------
No transition time violations found in the design.

*********************************************************************************
*
*
*  Maximum Capacitance Constraint Violations
*
*  Constraint Types:
*  S -> SDC constraint
*  C -> CLF/lib constraint
*  G -> Astro Global constraint
*
*********************************************************************************

Load cap    Constraint  MasterCell             Reason    Cell/Port Name
---------------------------------------------------------------------------------
0.1091    0.0353 G BUFCLKHD2X             PCP       U167ASTttcInst394/Z
0.0963    0.0353 G FFDRHDLX                            u_spi/BITcnt_reg_6_/QN
0.0940    0.0353 G BUFCLKHD2X             PCP       U169ASTttcInst396/Z
0.0843    0.0353 G BUFCLKHD2X             PCP       U42/Z
0.0840    0.0353 G BUFCLKHD2X             PCP       U87/Z
0.0835    0.0353 G BUFCLKHD2X             PCP       U54/Z
0.0801    0.0353 G BUFCLKHD2X             PCP       U44/Z
0.0801    0.0353 G BUFCLKHD2X             PCP       U99ASTttcInst488/Z
0.0796    0.0353 G BUFCLKHD2X             PCP       U39/Z
0.0791    0.0353 G BUFCLKHD2X             PCP       U97ASTttcInst484/Z
0.0771    0.0353 G BUFCLKHD2X             PCP       U40/Z
0.0764    0.0353 G BUFCLKHD2X             PCP       U46ASTttcInst496/Z
0.0744    0.0353 G BUFCLKHD2X             PCP       U142ASTttcInst454/Z
0.0743    0.0353 G BUFCLKHD2X             PCP       U62/Z
0.0741    0.0353 G BUFCLKHD2X             PCP       U89/Z
0.0739    0.0353 G BUFCLKHD2X             PCP       U45/Z
0.0735    0.0353 G BUFCLKHD2X             PCP       U80ASTttcInst458/Z
0.0727    0.0353 G BUFCLKHD2X             PCP       U129ASTttcInst415/Z
0.0725    0.0353 G BUFCLKHD2X             PCP       U60/Z
0.0725    0.0353 G BUFCLKHD2X             PCP       U141ASTttcInst451/Z
0.0724    0.0353 G BUFCLKHD2X             PCP       U61/Z
0.0723    0.0353 G BUFCLKHD2X             PCP       U43/Z
0.0723    0.0353 G BUFCLKHD2X             PCP       U52/Z
0.0721    0.0353 G BUFCLKHD2X             PCP       U145/Z
0.0720    0.0353 G BUFCLKHD2X             PCP       U138ASTttcInst442/Z
0.0719    0.0353 G BUFCLKHD2X             PCP       U92ASTttcInst568/Z
0.0716    0.0353 G BUFCLKHD2X             PCP       U143/Z
0.0715    0.0353 G BUFCLKHD2X             PCP       U53/Z
0.0715    0.0353 G BUFHD1X                            u_spi/BITcnt_reg_5_ASTttcInst174/Z
0.0714    0.0353 G BUFCLKHD2X             PCP       U57/Z
0.0714    0.0353 G BUFCLKHD2X             PCP       U90/Z
0.0714    0.0353 G BUFCLKHD2X                         U146/Z
0.0713    0.0353 G BUFCLKHD2X             PCP       U41/Z
0.0711    0.0353 G BUFCLKHD2X             PCP       U50/Z
0.0706    0.0353 G BUFCLKHD2X             PCP       U109/Z
0.0702    0.0353 G BUFCLKHD2X             PCP       U51/Z
0.0702    0.0353 G BUFCLKHD2X             PCP       U163ASTttcInst387/Z
0.0701    0.0353 G BUFCLKHD2X             PCP       U139ASTttcInst445/Z
0.0701    0.0353 G BUFHD2X                            u_spi/BITcnt_reg_6_ASTttcInst513/Z
0.0700    0.0353 G BUFCLKHD2X             PCP       U48/Z
0.0698    0.0353 G BUFCLKHD2X             PCP       U47/Z
0.0698    0.0353 G BUFCLKHD2X             PCP       U107/Z
0.0697    0.0353 G BUFCLKHD2X             PCP       U56/Z
0.0695    0.0353 G BUFCLKHD2X             PCP       U108/Z
0.0695    0.0353 G BUFCLKHD2X             PCP       U58/Z
0.0695    0.0353 G BUFCLKHD2X             PCP       U103/Z
0.0695    0.0353 G BUFCLKHD2X             PCP       U88/Z
0.0695    0.0353 G BUFCLKHD2X             PCP       U59/Z
0.0694    0.0353 G BUFCLKHD2X             PCP       U127ASTttcInst409/Z
0.0694    0.0353 G BUFCLKHD2X             PCP       U128ASTttcInst412/Z
0.0694    0.0353 G BUFCLKHD2X             PCP       U136ASTttcInst436/Z
0.0694    0.0353 G BUFCLKHD2X             PCP       U106/Z
0.0692    0.0353 G BUFCLKHD2X             PCP       U158ASTttcInst381/Z
0.0691    0.0353 G BUFCLKHD2X             PCP       U98ASTttcInst486/Z
0.0690    0.0353 G BUFCLKHD2X             PCP       U135ASTttcInst433/Z
0.0690    0.0353 G BUFCLKHD2X             PCP       U140ASTttcInst448/Z
0.0689    0.0353 G INVHDPX                DIS       U22/Z
0.0688    0.0353 G BUFCLKHD2X             PCP       U122/Z
0.0687    0.0353 G BUFCLKHD2X             PCP       U67/Z
0.0687    0.0353 G BUFCLKHD2X             PCP       U49/Z
0.0685    0.0353 G BUFCLKHD2X             PCP       U55/Z
0.0684    0.0353 G BUFHD2X                            u_spi/BITcnt_reg_6_ASTttcInst168/Z
0.0684    0.0353 G BUFCLKHD2X             PCP       U131ASTttcInst421/Z
0.0684    0.0353 G BUFCLKHD2X             PCP       U160ASTttcInst383/Z
0.0683    0.0353 G BUFCLKHD2X             PCP       U134ASTttcInst430/Z
0.0683    0.0353 G BUFCLKHD2X             PCP       U101ASTttcInst492/Z
0.0682    0.0353 G BUFCLKHD2X             PCP       U121/Z
0.0682    0.0353 G BUFCLKHD2X             PCP       U91/Z
0.0681    0.0353 G BUFCLKHD2X             PCP       U124/Z
0.0680    0.0353 G BUFCLKHD2X             PCP       U64/Z
0.0678    0.0353 G BUFHD2X                            u_spi/U938ASTttcInst122/Z
0.0677    0.0353 G BUFCLKHD2X             PCP       U105/Z
0.0676    0.0353 G INVHDPX                DIS       U24/Z
0.0676    0.0353 G BUFCLKHD2X             PCP       U93ASTttcInst476/Z
0.0676    0.0353 G BUFCLKHD2X             PCP       U65/Z
0.0675    0.0353 G BUFHD2X                            u_spi/BITcnt_reg_4_ASTttcInst178/Z
0.0673    0.0353 G BUFCLKHD2X             PCP       U63/Z
0.0673    0.0353 G INVHDPX                DIS       U30/Z
0.0671    0.0353 G BUFCLKHD2X             PCP       U85ASTttcInst468/Z
0.0671    0.0353 G BUFCLKHD2X             PCP       U144/Z
0.0671    0.0353 G BUFCLKHD2X             PCP       U130ASTttcInst418/Z
0.0670    0.0353 G BUFCLKHD2X             PCP       U66/Z
0.0670    0.0353 G BUFCLKHD2X             PCP       U104/Z
0.0670    0.0353 G BUFCLKHD2X             PCP       U86ASTttcInst470/Z
0.0669    0.0353 G BUFCLKHD2X             PCP       U70/Z
0.0669    0.0353 G BUFCLKHD2X             PCP       U111/Z
0.0668    0.0353 G BUFCLKHD2X             PCP       U132ASTttcInst424/Z
0.0668    0.0353 G BUFCLKHD2X             PCP       U68/Z
0.0668    0.0353 G BUFCLKHD2X             PCP       U123/Z
0.0665    0.0353 G INVHDPX                PCP       U147/Z
0.0664    0.0353 G BUFCLKHD2X             PCP       U126/Z
0.0664    0.0353 G BUFCLKHD2X             PCP       U102ASTttcInst494/Z
0.0664    0.0353 G BUFCLKHD2X             PCP       U95ASTttcInst480/Z
0.0664    0.0353 G BUFCLKHD2X             PCP       U83ASTttcInst464/Z
0.0663    0.0353 G BUFCLKHD2X             PCP       U96ASTttcInst482/Z
0.0662    0.0353 G BUFCLKHD2X             PCP       U94ASTttcInst478/Z
0.0662    0.0353 G BUFCLKHD2X             PCP       U74/Z
0.0662    0.0353 G BUFCLKHD2X             PCP       U75/Z
0.0662    0.0353 G BUFCLKHD2X             PCP       U69/Z
0.0662    0.0353 G BUFCLKHD2X             PCP       U125/Z
0.0661    0.0353 G BUFCLKHD2X             PCP       U78/Z
0.0661    0.0353 G INVHDPX                DIS       U36/Z
0.0661    0.0353 G BUFCLKHD2X             PCP       U165ASTttcInst389/Z
0.0661    0.0353 G BUFCLKHD2X             PCP       U100ASTttcInst490/Z
0.0660    0.0353 G INVHDPX                DIS       U26/Z
0.0660    0.0353 G BUFCLKHD2X             PCP       U79ASTttcInst456/Z
0.0660    0.0353 G INVHDPX                DIS       U34/Z
0.0660    0.0353 G BUFCLKHD2X             PCP       U81ASTttcInst460/Z
0.0659    0.0353 G BUFCLKHD2X             PCP       U82ASTttcInst462/Z
0.0659    0.0353 G BUFCLKHD2X             PCP       U133ASTttcInst427/Z
0.0659    0.0353 G BUFCLKHD2X             PCP       U84ASTttcInst466/Z
0.0658    0.0353 G BUFCLKHD2X             PCP       U166ASTttcInst392/Z
0.0658    0.0353 G BUFCLKHD2X             PCP       U77/Z
0.0658    0.0353 G BUFCLKHD2X             PCP       U118/Z
0.0658    0.0353 G BUFCLKHD2X             PCP       U137ASTttcInst439/Z
0.0658    0.0353 G BUFCLKHD2X             PCP       U71/Z
0.0658    0.0353 G INVHDPX                DIS       U32/Z
0.0658    0.0353 G BUFCLKHD2X             PCP       U73/Z
0.0657    0.0353 G INVHDPX                DIS       U28/Z
0.0657    0.0353 G BUFCLKHD2X             PCP       U76/Z
0.0655    0.0353 G BUFCLKHD2X             PCP       U117/Z
0.0655    0.0353 G BUFCLKHD2X             PCP       U114/Z
0.0654    0.0353 G BUFCLKHD2X             PCP       U120ASTttcInst405/Z
0.0654    0.0353 G FFDRHDLX                            u_spi/IRRreg_reg_30_/Q
0.0653    0.0353 G BUFCLKHD2X             PCP       U113/Z
0.0653    0.0353 G BUFCLKHD2X             PCP       U112/Z
0.0652    0.0353 G BUFCLKHD2X             PCP       U72/Z
0.0652    0.0353 G BUFCLKHD2X             PCP       U116/Z
0.0648    0.0353 G BUFCLKHD2X             PCP       U115/Z
0.0647    0.0353 G BUFCLKHD2X             PCP       U119ASTttcInst403/Z
0.0646    0.0353 G BUFCLKHD2X             PCP       U110/Z
0.0633    0.0353 G NOR2HDLX                            u_spi/U906/Z
0.0622    0.0353 G NAND3HDLX                         u_spi/U916/Z
0.0608    0.0353 G INVHDLX                            u_spi/U224/Z
0.0606    0.0353 G BUFHD2X                            u_spi/U341ASTttcInst189/Z
0.0604    0.0353 G INVHDLX                            u_spi/U188/Z
0.0592    0.0353 G INVCLKHD2X                         u_spi/U201/Z
0.0581    0.0353 G BUFHD2X                            u_spi/U938ASTttcInst520/Z
0.0580    0.0353 G BUFHD2X                            u_spi/U693ASTttcInst103/Z
0.0579    0.0353 G NAND3HDLX                         u_spi/U915/Z
0.0577    0.0353 G FFDRHDLX                            u_coda_regmap/reg08_reg_3_/Q
0.0572    0.0353 G INVHDLX                            u_spi/U187/Z
0.0569    0.0353 G BUFHD2X                            u_spi/U201ASTttcInst196/Z
0.0557    0.0353 G INVHDLX                            u_spi/U237/Z
0.0553    0.0353 G INVHDLX                            u_spi/U258/Z
0.0550    0.0353 G INVCLKHD4X                         u_spi/U450/Z
0.0547    0.0353 G FFDRHDLX                            u_coda_regmap/reg08_reg_0_/Q
0.0544    0.0353 G BUFHD2X                            u_spi/U341ASTttcInst188/Z
0.0543    0.0353 G INVHDLX                            u_coda_regmap/U50/Z
0.0541    0.0353 G INVHDLX                            u_spi/U222/Z
0.0537    0.0353 G FFDRHDLX                            u_spi/BITcnt_reg_0_/QN
0.0536    0.0353 G BUFHD2X                            u_spi/U936ASTttcInst180/Z
0.0534    0.0353 G FFDRHDLX                            u_spi/IRRreg_reg_29_/QN
0.0529    0.0353 G                                        I_sdi
0.0528    0.0353 G INVHDLX                            u_spi/U233/Z
0.0527    0.0353 G BUFCLKHD2X                         u_spi/U152ASThfnInst22/Z
0.0527    0.0353 G INVHDLX                            u_spi/U299/Z
0.0523    0.0353 G BUFHD1X                            u_spi/U938ASTttcInst121/Z
0.0522    0.0353 G BUFHD2X                            u_coda_regmap/toplevelASTttcInst148/Z
0.0522    0.0353 G FFDRHDLX                            u_coda_regmap/reg08_reg_6_/Q
0.0514    0.0353 G INVHDLX                            u_spi/U159/Z
0.0513    0.0353 G NOR2HDLX                            u_spi/U542/Z
0.0513    0.0353 G FFDRHDLX                            u_spi/BITcnt_reg_4_/QN
0.0512    0.0353 G OR3HD1X                            u_spi/U899/Z
0.0510    0.0353 G FFDRHDLX                            u_coda_regmap/reg08_reg_2_/Q
0.0508    0.0353 G FFDRHDLX                            u_spi/IRRreg_reg_31_/Q
0.0503    0.0353 G FFDRHDLX                            u_spi/BITcnt_reg_2_/QN
0.0502    0.0353 G INVHDLX                            u_spi/U435/Z
0.0501    0.0353 G BUFHD2X                            u_spi/U152ASTttcInst552/Z
0.0500    0.0353 G INVHDLX                            u_spi/U85/Z
0.0499    0.0353 G BUFHD2X                            u_spi/U78ASTttcInst162/Z
0.0496    0.0353 G BUFHD2X                            u_spi/U185ASTttcInst211/Z
0.0490    0.0353 G BUFHD2X                            u_spi/U366ASTttcInst208/Z
0.0489    0.0353 G INVHDLX                            u_spi/U263/Z
0.0487    0.0353 G INVHDLX                            u_spi/U91/Z
0.0487    0.0353 G NAND2HD1X                         u_spi/U50/Z
0.0484    0.0353 G BUFHD2X                            u_spi/U899ASTttcInst184/Z
0.0484    0.0353 G INVHDLX                            u_spi/U442/Z
0.0477    0.0353 G INVCLKHD4X                         u_spi/U226/Z
0.0472    0.0353 G INVHDLX                            u_spi/U128/Z
0.0471    0.0353 G INVHDLX                            u_spi/U133/Z
0.0470    0.0353 G BUFCLKHD2X                         u_spi/BITcnt_reg_6_ASTttcInst158/Z
0.0468    0.0353 G INVHDLX                            u_spi/U125/Z
0.0467    0.0353 G MUX4HDLX                            u_spi/U331/Z
0.0467    0.0353 G BUFHD2X                            u_spi/U366ASTttcInst204/Z
0.0466    0.0353 G BUFCLKHD2X                         U152/Z
0.0465    0.0353 G FFDRHDLX                            u_spi/BITcnt_reg_5_/QN
0.0461    0.0353 G INVHDLX                            u_coda_regmap/U84/Z
0.0460    0.0353 G INVHDLX                            u_spi/U152/Z
0.0457    0.0353 G NAND3HDLX                         u_spi/U346/Z
0.0457    0.0353 G NAND3B1HDLX                         u_spi/U347/Z
0.0456    0.0353 G BUFHD2X                            u_spi/U78ASTttcInst164/Z
0.0455    0.0353 G BUFHD2X                            u_spi/U366ASTttcInst207/Z
0.0454    0.0353 G INVCLKHD1X                         u_coda_regmap/U198/Z
0.0453    0.0353 G INVHDLX                            u_spi/U130/Z
0.0453    0.0353 G INVHDLX                            u_spi/U97/Z
0.0450    0.0353 G BUFHD2X                            u_spi/U72ASTttcInst512/Z
0.0447    0.0353 G INVHDLX                            u_spi/U225/Z
0.0446    0.0353 G BUFHD2X                            u_spi/U887ASTttcInst548/Z
0.0444    0.0353 G FFDRHDLX                            u_spi/BITcnt_reg_2_/Q
0.0443    0.0353 G BUFCLKHD2X                         u_spi/U22ASThfnInst14/Z
0.0442    0.0353 G BUFHD1X                            u_spi/U152ASTttcInst108/Z
0.0442    0.0353 G NAND2HD1X                         u_spi/U348/Z
0.0441    0.0353 G INVHDLX                            u_spi/U180/Z
0.0441    0.0353 G INVHDLX                            u_spi/U131/Z
0.0440    0.0353 G INVHDLX                            u_spi/U184/Z
0.0440    0.0353 G BUFHD2X                            u_spi/toplevelASTttcInst138/Z
0.0440    0.0353 G BUFHD2X                            u_spi/U72ASTttcInst172/Z
0.0435    0.0353 G BUFHD2X                            u_spi/U938ASTttcInst514/Z
0.0434    0.0353 G BUFHD2X                            U165ASTttcInst498/Z
0.0434    0.0353 G FFDRHDLX                            u_coda_regmap/reg08_reg_4_/Q
0.0432    0.0353 G BUFCLKHD2X                         u_spi/IRRreg_reg_30_ASTttcInst157/Z
0.0431    0.0353 G BUFCLKHD2X                         u_spi/U212ASTttcInst212/Z
0.0431    0.0353 G INVHDLX                            u_spi/U359/Z
0.0431    0.0353 G BUFHD2X                            u_spi/U366ASTttcInst203/Z
0.0430    0.0353 G BUFCLKHD2X                         u_spi/U226ASTttcInst215/Z
0.0428    0.0353 G BUFHD2X                            u_spi/toplevelASTttcInst141/Z
0.0427    0.0353 G FFDRHDLX                            u_spi/IRRreg_reg_27_/Q
0.0426    0.0353 G BUFCLKHD2X                         u_spi/U152ASTttcInst112/Z
0.0426    0.0353 G FFDRHDLX                            u_coda_regmap/reg07_reg_7_/Q
0.0425    0.0353 G BUFHD2X                            u_spi/U152ASTttcInst109/Z
0.0423    0.0353 G FFDRHDLX                            u_coda_regmap/reg02_reg_5_/Q
0.0422    0.0353 G BUFCLKHD2X                         u_myfifo/U161ASTttcInst64/Z
0.0421    0.0353 G BUFHD2X                            u_spi/U938ASTttcInst123/Z
0.0418    0.0353 G BUFHD2X                            u_coda_regmap/U212ASTttcInst244/Z
0.0417    0.0353 G BUFHD2X                            u_spi/U78ASTttcInst161/Z
0.0417    0.0353 G BUFHD2X                            u_coda_regmap/U253ASTttcInst225/Z
0.0417    0.0353 G BUFCLKHD2X                         u_coda_regmap/toplevelASTttcInst153/Z
0.0416    0.0353 G INVHDLX                            u_spi/U179/Z
0.0415    0.0353 G INVHD1X                            u_spi/U892/Z
0.0414    0.0353 G INVHDLX                            u_spi/U158/Z
0.0414    0.0353 G BUFHD2X                            u_spi/U201ASTttcInst508/Z
0.0412    0.0353 G MUX2HD1X                            u_spi/U366/Z
0.0412    0.0353 G INVHDLX                            u_spi/U95/Z
0.0412    0.0353 G MUX2HD1X                            u_spi/U30/Z
0.0410    0.0353 G BUFHD1X                            u_spi/BITcnt_reg_0_ASTttcInst156/Z
0.0409    0.0353 G BUFHD2X                            u_spi/U152ASTttcInst111/Z
0.0409    0.0353 G INVHDLX                            u_spi/U257/Z
0.0409    0.0353 G BUFHD2X                            u_spi/U366ASTttcInst210/Z
0.0408    0.0353 G FFDRHDLX                            u_coda_regmap/reg07_reg_2_/Q
0.0408    0.0353 G BUFCLKHD2X                         u_spi/U152ASThfnInst21/Z
0.0408    0.0353 G OR2HD1X                            u_spi/U47/Z
0.0407    0.0353 G FFDRHDLX                            u_spi/IRRreg_reg_31_/QN
0.0407    0.0353 G INVHDLX                            u_coda_regmap/U143/Z
0.0407    0.0353 G BUFHD2X                            u_spi/U201ASTttcInst509/Z
0.0407    0.0353 G FFDRHDLX                            u_coda_regmap/reg08_reg_5_/Q
0.0406    0.0353 G BUFHD1X                            u_spi/U152ASTttcInst106/Z
0.0405    0.0353 G INVHDLX                            u_spi/U444/Z
0.0405    0.0353 G BUFCLKHD2X                         u_spi/U226ASTttcInst217/Z
0.0404    0.0353 G INVHDLX                            u_spi/U98/Z
0.0402    0.0353 G INVCLKHD2X                         u_coda_regmap/U417/Z
0.0401    0.0353 G FFDRHDLX                            u_coda_regmap/reg0d_reg_5_/Q
0.0401    0.0353 G BUFHD2X                            u_spi/U212ASTttcInst213/Z
0.0401    0.0353 G BUFCLKHD2X                         u_myfifo/U484ASTttcInst343/Z
0.0399    0.0353 G BUFCLKHD2X                         u_coda_regmap/U19ASTttcInst275/Z
0.0398    0.0353 G FFDRHDLX                            u_spi/IRRreg_reg_28_/QN
0.0398    0.0353 G AOI211HD1X                         u_spi/U22/Z
0.0397    0.0353 G INVCLKHD4X                         u_spi/U185/Z
0.0396    0.0353 G AND3HD1X                            u_spi/U15/Z
0.0396    0.0353 G BUFHD2X                            u_spi/U366ASTttcInst506/Z
0.0396    0.0353 G INVHDLX                            u_myfifo/U321/Z
0.0395    0.0353 G BUFHD2X                            u_coda_regmap/U418ASTttcInst262/Z
0.0395    0.0353 G BUFHD2X                            u_spi/U938ASTttcInst118/Z
0.0394    0.0353 G BUFCLKHD2X                         u_spi/U936ASTttcInst182/Z
0.0394    0.0353 G BUFCLKHD2X                         u_myfifo/U481ASTttcInst340/Z
0.0393    0.0353 G NAND2HD1X                         u_spi/sub_462/U17/Z
0.0391    0.0353 G INVHDLX                            u_spi/U161/Z
0.0389    0.0353 G INVCLKHD4X                         u_spi/U78/Z
0.0388    0.0353 G BUFHD2X                            u_spi/U341ASTttcInst191/Z
0.0388    0.0353 G BUFHD2X                            u_myfifo/U316ASTttcInst73/Z
0.0386    0.0353 G BUFHD2X                            u_coda_regmap/O_fifo_to_reg_en_regASTttcInst243/Z
0.0385    0.0353 G FFDRHDLX                            u_coda_regmap/reg08_reg_7_/Q
0.0384    0.0353 G BUFHD1X                            u_spi/U938ASTttcInst120/Z
0.0383    0.0353 G BUFHD2X                            u_myfifo/U151ASTttcInst290/Z
0.0382    0.0353 G NAND4HD1X                         u_spi/U568/Z
0.0381    0.0353 G BUFCLKHD2X                         u_myfifo/U158ASTttcInst300/Z
0.0378    0.0353 G INVHDLX                            u_coda_regmap/U121/Z
0.0378    0.0353 G BUFHD2X                            u_myfifo/channel_reg_0_ASTttcInst325/Z
0.0377    0.0353 G BUFCLKHD2X                         u_spi/U22ASThfnInst13/Z
0.0377    0.0353 G FFDRHDLX                            u_spi/IRRreg_reg_0_/QN
0.0375    0.0353 G NAND2HDLX                         u_spi/U352/Z
0.0375    0.0353 G INVHDLX                            u_spi/U169/Z
0.0374    0.0353 G INVHDLX                            u_spi/U183/Z
0.0374    0.0353 G BUFCLKHD2X                         u_myfifo/U161ASTttcInst47/Z
0.0371    0.0353 G INVHDLX                            u_spi/U123/Z
0.0370    0.0353 G BUFHD2X                            u_spi/U366ASTttcInst205/Z
0.0370    0.0353 G BUFHD2X                            u_spi/U693ASTttcInst102/Z
0.0369    0.0353 G BUFCLKHD2X                         u_myfifo/U161ASTttcInst519/Z
0.0369    0.0353 G FFDRHDLX                            u_coda_regmap/reg07_reg_1_/Q
0.0368    0.0353 G INVHDLX                            u_spi/U938/Z
0.0367    0.0353 G NOR2HDLX                            u_spi/U664/Z
0.0366    0.0353 G INVHDLX                            u_spi/U207/Z
0.0365    0.0353 G BUFHD2X                            u_spi/toplevelASTttcInst523/Z
0.0364    0.0353 G BUFHD2X                            u_spi/U78ASTttcInst549/Z
0.0364    0.0353 G INVHDLX                            u_spi/U55/Z
0.0364    0.0353 G BUFHD2X                            u_myfifo/U161ASTttcInst540/Z
0.0364    0.0353 G BUFCLKHD2X                         u_coda_regmap/U418ASTttcInst260/Z
0.0363    0.0353 G BUFHD2X                            u_myfifo/U316ASTttcInst79/Z
0.0363    0.0353 G BUFHD2X                            u_spi/U355ASTttcInst193/Z
0.0363    0.0353 G BUFHD2X                            u_coda_regmap/toplevelASTttcInst149/Z
0.0363    0.0353 G BUFHD2X                            u_coda_regmap/toplevelASTttcInst154/Z
0.0363    0.0353 G BUFCLKHD2X                         u_coda_regmap/U299ASTttcInst265/Z
0.0363    0.0353 G INVHDLX                            u_spi/U300/Z
0.0363    0.0353 G BUFCLKHD2X                         u_spi/U6ASTttcInst113/Z
0.0362    0.0353 G FFDRHDLX                            u_coda_regmap/regc2_reg_4_/Q
0.0362    0.0353 G BUFCLKHD2X                         u_myfifo/U158ASTttcInst302/Z
0.0362    0.0353 G BUFHD2X                            toplevelASTttcInst176/Z
0.0361    0.0353 G BUFCLKHD2X                         u_myfifo/U161ASTttcInst55/Z
0.0361    0.0353 G BUFCLKHD2X                         u_myfifo/U161ASTttcInst48/Z
0.0360    0.0353 G BUFCLKHD2X                         u_myfifo/channel_reg_2_ASTttcInst399/Z
0.0360    0.0353 G BUFHD2X                            u_coda_regmap/U204ASTttcInst263/Z
0.0360    0.0353 G BUFHD2X                            u_spi/U938ASTttcInst124/Z
0.0360    0.0353 G AND3HD1X                            u_coda_regmap/U36/Z
0.0360    0.0353 G BUFCLKHD2X                         u_coda_regmap/U42/Z
0.0360    0.0353 G BUFCLKHD2X                         u_coda_regmap/U43/Z
0.0360    0.0353 G MUX2HD1X                            u_spi/U35/Z
0.0359    0.0353 G INVHDPX                            u_spi/U848/Z
0.0359    0.0353 G BUFHD2X                            u_spi/U693ASTttcInst104/Z
0.0359    0.0353 G INVHDLX                            u_spi/U177/Z
0.0358    0.0353 G INVHDLX                            u_spi/U136/Z
0.0358    0.0353 G BUFHD2X                            u_myfifo/U487ASTttcInst351/Z
0.0357    0.0353 G BUFCLKHD2X                         u_myfifo/U20ASTttcInst313/Z
0.0357    0.0353 G BUFCLKHD2X                         u_myfifo/U113ASTttcInst318/Z
0.0357    0.0353 G BUFCLKHD2X                         u_coda_regmap/toplevelASTttcInst155/Z
0.0357    0.0353 G BUFCLKHD2X                         u_myfifo/U514ASTttcInst303/Z
0.0357    0.0353 G BUFHD2X                            u_spi/U938ASTttcInst125/Z
0.0357    0.0353 G BUFHD2X                            u_myfifo/U165ASTttcInst329/Z
0.0357    0.0353 G NOR2HDLX                            u_spi/U321/Z
0.0357    0.0353 G BUFHD2X                            u_spi/U22ASTttcInst126/Z
0.0356    0.0353 G INVHDLX                            u_myfifo/U166/Z
0.0356    0.0353 G INVHDLX                            u_spi/U209/Z
0.0356    0.0353 G BUFCLKHD2X                         u_spi/U22ASTttcInst130/Z
0.0356    0.0353 G BUFCLKHD2X                         u_myfifo/U161ASTttcInst52/Z
0.0354    0.0353 G FFDRHDLX                            u_spi/SerBits_reg_1_/Q

There are 334 Max capacitance violations on 334 nets.

电小白 · 发表于 2018-3-30 20:00:41

回复 1# xiaoming233

本人愚见
应该先把Max cap解掉吧，然后再去看timing。
不过hold 这么大，如果PR问题不是很大的情况下，多半是约束的问题。

xiaoming233 · 发表于 2018-4-8 18:47:29

回复 2# 电小白

谢谢！我后来发现是我时序的约束有问题，现在setup和hold都没有报错了，但是max capacitance报错一直在，请问这个问题该如何解决呢，一直放款max cap的约束就可以吗？

xingyun620 · 发表于 2018-4-9 10:23:06

本帖最后由 xingyun620 于 2018-4-9 10:24 编辑

你这cap是sdc里约束的吧？其实没有max_transition问题就还好，因为lib里卡的cap没这么小。另外怎么还在用astro，太古老了...有条件的话换icc或者innovus吧

电小白 · 发表于 2018-4-9 17:12:46

回复 3# xiaoming233

如果有Tweaker，看看是否可以auto_fix掉，如果没有这种工具的话，应该只能手动修了。

verifyboy · 发表于 2021-10-12 00:36:18

thanks

[求助] 新手求助各位前辈，Astro跑后端时如何消除hold time violation

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