verilog RTL coding, of synthesisible code

xiaoyisimonguo · 发表于 2018-2-20 02:15:51

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do we have a way to declare mutex, mutually exclusive, in verilog RTL, of synthesizable codeor in Design compiler runs to set constraints?

Many thanks
---------------my RTL code---------
always @(posedge phck[0] or negedge reset_)
   begin
      if(!reset_)
      begin
         reg_phck[0] <= 0 ;
         reg_phck[1] <= 0 ;
         reg_phck[2] <= 0 ;
         reg_phck[3] <= 0 ;
      end
      else
      begin
            reg_phck[0] <= reg4dq_in[0] ;
            reg_phck[1] <= reg4dq_in[16] ;
            reg_phck[2] <= reg4dq_in[32] ;
            reg_phck[3] <= reg4dq_in[48] ;
      end
  end
always @(posedge phck_[0] or negedge reset_)
   begin
      if(!reset_)
      begin
         reg_phck[0] <= 0 ;

         reg_phck[1] <= 0 ;
         reg_phck[2] <= 0 ;
         reg_phck[3] <= 0 ;
      end
      else
      begin
            reg_phck[0] <= reg4dq_in[1] ;
            reg_phck[1] <= reg4dq_in[17] ;
            reg_phck[2] <= reg4dq_in[33] ;
            reg_phck[3] <= reg4dq_in[49] ;
      end
  end

-----------------end of RTL code inclusion-----------

When I tried to read in  the code:
read_verilog ../ref/fifo_rtl/readfifo64to4.v
I got the
Error:  /home/dubeeloo/proj/dDesign/DFTcompiler/ref/fifo_rtl/readfifo64to4.v:53: Net 'reg_phck[3]' or a directly
connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366)

but I know phck[0] and phck_[0] are mutually exclusive, they would not have rising edge at the same time