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本帖最后由 13804576693 于 2018-1-5 21:18 编辑
LVS 出现一些错误，大神帮忙看一下怎么回事，报错管子的宽长版图和原理图都差一点，这是怎么回事呢？多谢了！！！！
LVS Netlist Compiler - Errors and Warnings for "/home/boshi51/digital_QRS/clk/all.cdl"
--------------------------------------------------------------------------------------
Warning: Duplicate subckt definition "POST_DRIVER_16" at line 1296 in file "/home/boshi51/digital_QRS/clk/HDIOH2ING01V1.cdl"
##################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## L V S R E P O R T ##
## ##
##################################################
REPORT FILE NAME: clk.lvs.report
LAYOUT NAME: /home/boshi51/newpdk/HHGRACE_PDK_BCD350GE/tech/clk.sp ('clk')
SOURCE NAME: /home/boshi51/digital_QRS/clk/all.cdl ('clk')
RULE FILE: /home/boshi51/newpdk/HHGRACE_PDK_BCD350GE/tech/_be35_5.0v+40v_1p4m_calibre_lvs_v1.7_
CREATION TIME: Fri Jan 5 19:04:40 2018
CURRENT DIRECTORY: /home/boshi51/newpdk/HHGRACE_PDK_BCD350GE/tech
USER NAME: boshi51
CALIBRE VERSION: v2011.2_34.26 Wed Jul 6 05:20:56 PDT 2011
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Property errors.
Warning: Unbalanced smashed mosfets were matched.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT clk clk
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME "VDD" "?VDD?" "VCC" "?VCC?"
LVS GROUND NAME "GND" "?GND?" "VSS" "?VSS?"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE NO
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS FLATTEN INSIDE CELL NO
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS YES
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE YES
SOURCE CASE YES
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 32
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Device Type Map
LVS DEVICE TYPE RESISTOR "RW" [ POS=POS NEG=NEG ] SOURCE LAYOUT
// Reduction
LVS REDUCE SERIES MOS YES
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES NO
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCE D(ZN) PARALLEL
LVS REDUCE PC PARALLEL
LVS REDUCE J(NJ) PARALLEL
LVS REDUCTION PRIORITY PARALLEL
LVS SHORT EQUIVALENT NODES NO
// Trace Property
TRACE PROPERTY q(4l) a a 1
TRACE PROPERTY q(pn) a a 1
TRACE PROPERTY q(vp) a a 1
TRACE PROPERTY q(4n) a a 1
TRACE PROPERTY q(4k) a a 1
TRACE PROPERTY q(p4) a a 1
TRACE PROPERTY m(sn) w w 0
TRACE PROPERTY m(sn) l l 0
TRACE PROPERTY m(sp) w w 0
TRACE PROPERTY m(sp) l l 0
TRACE PROPERTY m(mn) w w 0
TRACE PROPERTY m(mn) l l 0
TRACE PROPERTY md(de) w w 0
TRACE PROPERTY md(de) l l 0
TRACE PROPERTY m(snh) w w 0
TRACE PROPERTY m(snh) l l 0
TRACE PROPERTY m(sph) w w 0
TRACE PROPERTY m(sph) l l 0
TRACE PROPERTY m(mnh) w w 0
TRACE PROPERTY m(mnh) l l 0
TRACE PROPERTY md(deh) w w 0
TRACE PROPERTY md(deh) l l 0
TRACE PROPERTY m(2s) w w 0
TRACE PROPERTY m(2s) l l 0
TRACE PROPERTY m(4s) w w 0
TRACE PROPERTY m(4s) l l 0
TRACE PROPERTY m(h2) w w 0
TRACE PROPERTY m(h2) l l 0
TRACE PROPERTY m(so) w w 0
TRACE PROPERTY m(so) l l 0
TRACE PROPERTY ldd(i2) w w 0
TRACE PROPERTY ldd(i2) l l 0
TRACE PROPERTY ldd(i4) w w 0
TRACE PROPERTY ldd(i4) l l 0
TRACE PROPERTY lddd(dn4) w w 0
TRACE PROPERTY lddd(dn4) l l 0
TRACE PROPERTY ldd(xn) w w 0
TRACE PROPERTY ldd(xn) l l 0
TRACE PROPERTY ldd(x4) w w 0
TRACE PROPERTY ldd(x4) l l 0
TRACE PROPERTY ldd(ap) w w 0
TRACE PROPERTY ldd(ap) l l 0
TRACE PROPERTY ldd(4p) w w 0
TRACE PROPERTY ldd(4p) l l 0
TRACE PROPERTY ldd(ao) w w 0
TRACE PROPERTY ldd(ao) l l 0
TRACE PROPERTY ldd(4o) w w 0
TRACE PROPERTY ldd(4o) l l 0
TRACE PROPERTY ldd(sp24) w w 0
TRACE PROPERTY ldd(sp24) l l 0
TRACE PROPERTY ldd(sp30) w w 0
TRACE PROPERTY ldd(sp30) l l 0
TRACE PROPERTY ldd(sph30) w w 0
TRACE PROPERTY ldd(sph30) l l 0
TRACE PROPERTY ldd(sph40) w w 0
TRACE PROPERTY ldd(sph40) l l 0
TRACE PROPERTY ldd(snl24) w w 0
TRACE PROPERTY ldd(snl24) l l 0
TRACE PROPERTY ldd(snd12) w w 0
TRACE PROPERTY ldd(snd12) l l 0
TRACE PROPERTY ldd(snl30) w w 0
TRACE PROPERTY ldd(snl30) l l 0
TRACE PROPERTY ldd(snl40) w w 0
TRACE PROPERTY ldd(snl40) l l 0
TRACE PROPERTY ldd(snh30) w w 0
TRACE PROPERTY ldd(snh30) l l 0
TRACE PROPERTY ldd(snh40) w w 0
TRACE PROPERTY ldd(snh40) l l 0
TRACE PROPERTY mn(nn) w w 0
TRACE PROPERTY mn(nn) l l 0
TRACE PROPERTY mn(np) w w 0
TRACE PROPERTY mn(np) l l 0
TRACE PROPERTY mn(nm) w w 0
TRACE PROPERTY mn(nm) l l 0
TRACE PROPERTY mn(nd) w w 0
TRACE PROPERTY mn(nd) l l 0
TRACE PROPERTY m(op) w w 0
TRACE PROPERTY m(op) l l 0
TRACE PROPERTY m(s2) w w 0
TRACE PROPERTY m(s2) l l 0
TRACE PROPERTY m(s4) w w 0
TRACE PROPERTY m(s4) l l 0
TRACE PROPERTY m(vs) w w 0
TRACE PROPERTY m(vs) l l 0
TRACE PROPERTY ldde(e1) w w 0
TRACE PROPERTY ldde(e1) l l 0
TRACE PROPERTY ldde(e2) w w 0
TRACE PROPERTY ldde(e2) l l 0
TRACE PROPERTY ldde(e1n) w w 0
TRACE PROPERTY ldde(e1n) l l 0
TRACE PROPERTY ldde(e2n) w w 0
TRACE PROPERTY ldde(e2n) l l 0
TRACE PROPERTY ldde(ec) w w 0
TRACE PROPERTY ldde(ec) l l 0
TRACE PROPERTY ldde(ei) w w 0
TRACE PROPERTY ldde(ei) l l 0
TRACE PROPERTY ldde(ef) w w 0
TRACE PROPERTY ldde(ef) l l 0
TRACE PROPERTY ldde(eh) w w 0
TRACE PROPERTY ldde(eh) l l 0
TRACE PROPERTY j(nj) w jft_w 0
TRACE PROPERTY j(nj) l jft_l 0
TRACE PROPERTY d(d1) a a 1
TRACE PROPERTY d(d3) a a 1
TRACE PROPERTY d(d2) a a 1
TRACE PROPERTY d(zn) m m 0
TRACE PROPERTY c(c3) c c 1
TRACE PROPERTY c(c1) c c 1
TRACE PROPERTY c(c2) c c 1
TRACE PROPERTY pc c c 1
TRACE PROPERTY c(nc) c c 1
TRACE PROPERTY r(rh) r r 1
TRACE PROPERTY r(rm) r r 1
TRACE PROPERTY r(no) r r 1
TRACE PROPERTY r(po) r r 1
TRACE PROPERTY r(rn) r r 1
TRACE PROPERTY r(nr) r r 1
TRACE PROPERTY r(r1) r r 1
TRACE PROPERTY rw r r 1
TRACE PROPERTY r(fu) r r 1
TRACE PROPERTY r(r2) r r 1
TRACE PROPERTY r(r3) r r 1
TRACE PROPERTY r(r4) r r 1
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Property errors.
Warning: Unbalanced smashed mosfets were matched.
LAYOUT CELL NAME: clk
SOURCE CELL NAME: clk
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 8 8
Nets: 98 99 *
Instances: 274 279 * M (4 pins)
------ ------
Total Inst: 274 279
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 8 8
Nets: 73 73
Instances: 154 154 M (4 pins)
20 20 SM2 (4 pins)
1 1 SM3 (5 pins)
3 3 SPM_2_1 (5 pins)
------ ------
Total Inst: 178 178
* = Number of objects in layout different from number in source.
**************************************************************************************************************
PROPERTY ERRORS
DISC# LAYOUT SOURCE ERROR
**************************************************************************************************************
1 M90(92.510,43.320) M(SP) XU6/M3 M(sp)
l: 0.500141 u l: 0.5 u 0.0282%
w: 4.10284 u w: 4.1 u 0.0693%
2 M77(85.810,45.370) M(SP) XU6/M2 M(sp)
l: 0.500161 u l: 0.5 u 0.0322%
w: 3.60284 u w: 3.6 u 0.0789%
3 M80(87.110,43.820) M(SP) XU6/M1 M(sp)
l: 0.500161 u l: 0.5 u 0.0322%
w: 3.60284 u w: 3.6 u 0.0789%
4 M74(81.550,45.350) M(SP) XU10/M1I4 M(sp)
l: 0.500138 u l: 0.5 u 0.0276%
w: 3.15213 u w: 3.15 u 0.0676%
5 M75(82.900,44.390) M(SP) XU10/M1I3 M(sp)
l: 0.500161 u l: 0.5 u 0.0322%
w: 2.70213 u w: 2.7 u 0.0789%
6 M38(104.570,56.100) M(SN) XFE_PHC0_freq_div_1/MX1I6_M1I2_0 M(sn)
l: 0.500451 u l: 0.5 u 0.0902%
w: 2.50154 u w: 2.5 u 0.0616%
7 M52(116.570,76.560) M(SN) Xfreq_div_reg_1_/M31 M(sn)
l: 0.500701 u l: 0.5 u 0.14%
w: 2.60095 u w: 2.6 u 0.0365%
8 M55(118.600,75.120) M(SN) Xfreq_div_reg_1_/M30 M(sn)
l: 0.500932 u l: 0.5 u 0.186%
w: 2.70037 u w: 2.7 u 0.0137%
9 M60(122.520,80.230) M(SN) Xclk__L1_I0/MX1I10_M1I2_28 M(sn)
l: 0.500285 u l: 0.5 u 0.0571%
w: 62.4116 u w: 62.4 u 0.0187%
10 M67(128.040,80.350) M(SN) Xclk__L1_I0/MX1I6_M1I2_2 M(sn)
l: 0.500306 u l: 0.5 u 0.0612%
w: 8.32452 u w: 8.32 u 0.0543%
11 M128(122.520,88.560) M(SP) Xclk__L1_I0/MX1I10_M1I1_28 M(sp)
l: 0.500124 u l: 0.5 u 0.0248%
w: 143.392 u w: 143.4 u 0.00582%
12 M135(128.040,88.560) M(SP) Xclk__L1_I0/MX1I6_M1I1_2 M(sp)
l: 0.500133 u l: 0.5 u 0.0266%
w: 19.1245 u w: 19.12 u 0.0236%
13 X155/M5(65.190,52.380) M(SN) Xfreq_div_reg_3_/M32 M(sn)
l: 0.500451 u l: 0.5 u 0.0902%
w: 2.50154 u w: 2.5 u 0.0616%
14 X155/M6(63.400,51.060) M(SN) Xfreq_div_reg_3_/M33 M(sn)
l: 0.500451 u l: 0.5 u 0.0902%
w: 2.50154 u w: 2.5 u 0.0616%
15 X155/M14(45.170,52.260) M(SN) Xfreq_div_reg_3_/M18_0 M(sn)
l: 0.500259 u l: 0.5 u 0.0518%
w: 4.79811 u w: 4.8 u 0.0394%
16 X155/M29(45.230,44.690) M(SP) Xfreq_div_reg_3_/M1_0 M(sp)
l: 0.500175 u l: 0.5 u 0.0349%
w: 8.10296 u w: 8.1 u 0.0366%
17 X156/M5(70.390,79.860) M(SN) Xfreq_div_reg_2_/M32 M(sn)
l: 0.500451 u l: 0.5 u 0.0902%
w: 2.50154 u w: 2.5 u 0.0616%
18 X156/M6(68.600,81.180) M(SN) Xfreq_div_reg_2_/M33 M(sn)
l: 0.500451 u l: 0.5 u 0.0902%
w: 2.50154 u w: 2.5 u 0.0616%
19 X156/M14(50.370,79.980) M(SN) Xfreq_div_reg_2_/M18_0 M(sn)
l: 0.500259 u l: 0.5 u 0.0518%
w: 4.79811 u w: 4.8 u 0.0394%
20 X156/M29(50.430,87.550) M(SP) Xfreq_div_reg_2_/M1_0 M(sp)
l: 0.500175 u l: 0.5 u 0.0349%
w: 8.10296 u w: 8.1 u 0.0366%
21 X157/M5(75.590,54.780) M(SN) Xfreq_div_reg_0_/M32 M(sn)
l: 0.500451 u l: 0.5 u 0.0902%
w: 2.50154 u w: 2.5 u 0.0616%
22 X157/M6(73.800,56.100) M(SN) Xfreq_div_reg_0_/M33 M(sn)
l: 0.500451 u l: 0.5 u 0.0902%
w: 2.50154 u w: 2.5 u 0.0616%
23 X157/M14(55.570,54.900) M(SN) Xfreq_div_reg_0_/M18_0 M(sn)
l: 0.500259 u l: 0.5 u 0.0518%
w: 4.79811 u w: 4.8 u 0.0394%
24 X157/M29(55.630,62.470) M(SP) Xfreq_div_reg_0_/M1_0 M(sp)
l: 0.500175 u l: 0.5 u 0.0349%
w: 8.10296 u w: 8.1 u 0.0366%
25 X158/M5(117.190,52.380) M(SN) Xfreq_div_reg_4_/M32 M(sn)
l: 0.500451 u l: 0.5 u 0.0902%
w: 2.50154 u w: 2.5 u 0.0616%
26 X158/M6(115.400,51.060) M(SN) Xfreq_div_reg_4_/M33 M(sn)
l: 0.500451 u l: 0.5 u 0.0902%
w: 2.50154 u w: 2.5 u 0.0616%
27 X158/M14(97.170,52.260) M(SN) Xfreq_div_reg_4_/M18_0 M(sn)
l: 0.500259 u l: 0.5 u 0.0518%
w: 4.79811 u w: 4.8 u 0.0394%
28 X158/M29(97.230,44.690) M(SP) Xfreq_div_reg_4_/M1_0 M(sp)
l: 0.500175 u l: 0.5 u 0.0349%
w: 8.10296 u w: 8.1 u 0.0366%
29 M9(85.810,49.900) M(SN) XU6/M7 M(sn)
l: 0.500246 u l: 0.5 u 0.0492%
w: 2.35284 u w: 2.35 u 0.121%
30 M12(86.810,49.900) M(SN) XU6/M6 M(sn)
l: 0.500246 u l: 0.5 u 0.0492%
w: 2.35284 u w: 2.35 u 0.121%
31 M20(91.210,49.900) M(SN) XU6/M10 M(sn)
l: 0.500282 u l: 0.5 u 0.0564%
w: 2.05284 u w: 2.05 u 0.139%
32 M16(89.710,50.900) M(SN) XU6/M9 M(sn)
l: 0.500282 u l: 0.5 u 0.0564%
w: 2.05284 u w: 2.05 u 0.139%
33 M23(92.710,49.900) M(SN) XU6/M8 M(sn)
l: 0.500269 u l: 0.5 u 0.0538%
w: 2.15284 u w: 2.15 u 0.132%
34 M64(124.470,76.850) M(SN) Xfreq_div_reg_1_/M22 M(sn)
l: 0.501323 u l: 0.5 u 0.265%
w: 2.88676 u w: 2.9 u 0.457%
35 M65(125.900,76.850) M(SN) Xfreq_div_reg_1_/M24 M(sn)
l: 0.501323 u l: 0.5 u 0.265%
w: 2.88676 u w: 2.9 u 0.457%
36 X155/M0(73.265,50.860) M(SN) Xfreq_div_reg_3_/M24 M(sn)
l: 0.501156 u l: 0.5 u 0.231%
w: 2.80392 u w: 2.8 u 0.14%
37 X155/M1(71.835,50.860) M(SN) Xfreq_div_reg_3_/M22 M(sn)
l: 0.501156 u l: 0.5 u 0.231%
w: 2.80392 u w: 2.8 u 0.14%
38 X155/M10(52.870,52.330) M(SN) Xfreq_div_reg_3_/M20 M(sn)
l: 0.500715 u l: 0.5 u 0.143%
w: 2.55095 u w: 2.55 u 0.0373%
39 X155/M11(51.570,52.330) M(SN) Xfreq_div_reg_3_/M21 M(sn)
l: 0.500715 u l: 0.5 u 0.143%
w: 2.55095 u w: 2.55 u 0.0373%
40 X156/M0(78.465,81.380) M(SN) Xfreq_div_reg_2_/M24 M(sn)
l: 0.501156 u l: 0.5 u 0.231%
w: 2.80392 u w: 2.8 u 0.14%
41 X156/M1(77.035,81.380) M(SN) Xfreq_div_reg_2_/M22 M(sn)
l: 0.501156 u l: 0.5 u 0.231%
w: 2.80392 u w: 2.8 u 0.14%
42 X156/M10(58.070,79.910) M(SN) Xfreq_div_reg_2_/M20 M(sn)
l: 0.500715 u l: 0.5 u 0.143%
w: 2.55095 u w: 2.55 u 0.0373%
43 X156/M11(56.770,79.910) M(SN) Xfreq_div_reg_2_/M21 M(sn)
l: 0.500715 u l: 0.5 u 0.143%
w: 2.55095 u w: 2.55 u 0.0373%
44 X157/M0(83.665,56.300) M(SN) Xfreq_div_reg_0_/M24 M(sn)
l: 0.501156 u l: 0.5 u 0.231%
w: 2.80392 u w: 2.8 u 0.14%
45 X157/M1(82.235,56.300) M(SN) Xfreq_div_reg_0_/M22 M(sn)
l: 0.501156 u l: 0.5 u 0.231%
w: 2.80392 u w: 2.8 u 0.14%
46 X157/M10(63.270,54.830) M(SN) Xfreq_div_reg_0_/M20 M(sn)
l: 0.500715 u l: 0.5 u 0.143%
w: 2.55095 u w: 2.55 u 0.0373%
47 X157/M11(61.970,54.830) M(SN) Xfreq_div_reg_0_/M21 M(sn)
l: 0.500715 u l: 0.5 u 0.143%
w: 2.55095 u w: 2.55 u 0.0373%
48 X158/M0(125.265,50.860) M(SN) Xfreq_div_reg_4_/M24 M(sn)
l: 0.501156 u l: 0.5 u 0.231%
w: 2.80392 u w: 2.8 u 0.14%
49 X158/M1(123.835,50.860) M(SN) Xfreq_div_reg_4_/M22 M(sn)
l: 0.501156 u l: 0.5 u 0.231%
w: 2.80392 u w: 2.8 u 0.14%
50 X158/M10(104.870,52.330) M(SN) Xfreq_div_reg_4_/M20 M(sn)
l: 0.500715 u l: 0.5 u 0.143%
w: 2.55095 u w: 2.55 u 0.0373%
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 8 8 0 0
Nets: 73 73 0 0
Instances: 64 64 0 0 M(sn)
90 90 0 0 M(sp)
20 20 0 0 SM2
1 1 0 0 SM3
3 3 0 0 SPM_2_1
------- ------- --------- ---------
Total Inst: 178 178 0 0
o Statistics:
80 layout mos transistors were reduced to 12.
68 mos transistors were deleted by parallel reduction.
86 source mos transistors were reduced to 13.
73 mos transistors were deleted by parallel reduction.
o Initial Correspondence Points:
Ports: VCC VSS clk clk_div16 clk_div8 clk_div2 clk_div32 rstn
o Matched Mosfets Which Have Been Unequally Reduced:
M128(122.520,88.560) Xclk__L1_I0/MX1I10_M1I1_28
M76(85.360,84.970) Xclk__L1_I0/MX1I10_M1I1
M78(86.640,88.560) Xclk__L1_I0/MX1I10_M1I1_0
M82(88.120,84.970) Xclk__L1_I0/MX1I10_M1I1_1
M83(89.400,88.560) Xclk__L1_I0/MX1I10_M1I1_2
M86(90.880,84.970) Xclk__L1_I0/MX1I10_M1I1_3
M89(92.160,88.560) Xclk__L1_I0/MX1I10_M1I1_4
M92(93.640,84.970) Xclk__L1_I0/MX1I10_M1I1_5
M93(94.920,88.560) Xclk__L1_I0/MX1I10_M1I1_6
M94(96.400,84.970) Xclk__L1_I0/MX1I10_M1I1_7
M96(97.680,88.560) Xclk__L1_I0/MX1I10_M1I1_8
M98(99.160,84.970) Xclk__L1_I0/MX1I10_M1I1_9
M100(100.440,88.560) Xclk__L1_I0/MX1I10_M1I1_10
M102(101.920,84.970) Xclk__L1_I0/MX1I10_M1I1_11
M104(103.200,88.560) Xclk__L1_I0/MX1I10_M1I1_12
M107(104.680,84.970) Xclk__L1_I0/MX1I10_M1I1_13
M109(105.960,88.560) Xclk__L1_I0/MX1I10_M1I1_14
M110(107.440,84.970) Xclk__L1_I0/MX1I10_M1I1_15
M111(108.720,88.560) Xclk__L1_I0/MX1I10_M1I1_16
M113(110.200,84.970) Xclk__L1_I0/MX1I10_M1I1_17
M115(111.480,88.560) Xclk__L1_I0/MX1I10_M1I1_18
M116(112.960,84.970) Xclk__L1_I0/MX1I10_M1I1_19
M118(114.240,88.560) Xclk__L1_I0/MX1I10_M1I1_20
M120(115.720,84.970) Xclk__L1_I0/MX1I10_M1I1_21
M121(117.000,88.560) Xclk__L1_I0/MX1I10_M1I1_22
M123(118.480,84.970) Xclk__L1_I0/MX1I10_M1I1_23
M124(119.760,88.560) Xclk__L1_I0/MX1I10_M1I1_24
M126(121.240,84.970) Xclk__L1_I0/MX1I10_M1I1_25
** missing smashed mosfet ** Xclk__L1_I0/MX1I10_M1I1_26
** missing smashed mosfet ** Xclk__L1_I0/MX1I10_M1I1_27
M60(122.520,80.230) Xclk__L1_I0/MX1I10_M1I2_28
M8(85.360,81.020) Xclk__L1_I0/MX1I10_M1I2
M10(86.640,80.200) Xclk__L1_I0/MX1I10_M1I2_0
M14(88.120,81.020) Xclk__L1_I0/MX1I10_M1I2_1
M15(89.400,80.200) Xclk__L1_I0/MX1I10_M1I2_2
M18(90.880,81.020) Xclk__L1_I0/MX1I10_M1I2_3
M21(92.160,80.200) Xclk__L1_I0/MX1I10_M1I2_4
M24(93.640,81.020) Xclk__L1_I0/MX1I10_M1I2_5
M25(94.920,80.200) Xclk__L1_I0/MX1I10_M1I2_6
M26(96.400,81.020) Xclk__L1_I0/MX1I10_M1I2_7
M28(97.680,80.200) Xclk__L1_I0/MX1I10_M1I2_8
M30(99.160,81.020) Xclk__L1_I0/MX1I10_M1I2_9
M32(100.440,80.200) Xclk__L1_I0/MX1I10_M1I2_10
M34(101.920,81.020) Xclk__L1_I0/MX1I10_M1I2_11
M36(103.200,80.200) Xclk__L1_I0/MX1I10_M1I2_12
M39(104.680,81.020) Xclk__L1_I0/MX1I10_M1I2_13
M41(105.960,80.200) Xclk__L1_I0/MX1I10_M1I2_14
M42(107.440,81.020) Xclk__L1_I0/MX1I10_M1I2_15
M44(108.720,80.200) Xclk__L1_I0/MX1I10_M1I2_16
M45(110.200,81.020) Xclk__L1_I0/MX1I10_M1I2_17
M47(111.480,80.200) Xclk__L1_I0/MX1I10_M1I2_18
M48(112.960,81.020) Xclk__L1_I0/MX1I10_M1I2_19
M50(114.240,80.200) Xclk__L1_I0/MX1I10_M1I2_20
M51(115.720,81.020) Xclk__L1_I0/MX1I10_M1I2_21
M53(117.000,80.200) Xclk__L1_I0/MX1I10_M1I2_22
M54(118.480,81.020) Xclk__L1_I0/MX1I10_M1I2_23
M56(119.760,80.200) Xclk__L1_I0/MX1I10_M1I2_24
M58(121.240,81.020) Xclk__L1_I0/MX1I10_M1I2_25
** missing smashed mosfet ** Xclk__L1_I0/MX1I10_M1I2_26
** missing smashed mosfet ** Xclk__L1_I0/MX1I10_M1I2_27
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time: 0 sec
Total Elapsed Time: 0 sec |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2018-1-5 19:18:08
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