(1)A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW
(2)An 11.0 bit ENOB, 9.8 fJ/conv.-step noise-shaping SAR ADC calibrated by least squares estimation
(3)A Fully Passive Compressive Sensing SAR ADC for Low-Power Wireless Sensors
(4)An 84 dB dynamic range 62.5–625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier
(5)A supposedly clever thing i'll never do again, Custom Integrated Circuits Conference (CICC), 2017 IEEE,这篇很扯淡,所以更想看。
(6)A Low Power Multi-channel Input Delta-Sigma ADC without Reset