北京数字设计项目经理（数字设计，验证等岗位都有）

hamy

有兴趣的可以发简历hamy@hibohr.com，或者加微信13512136297沟通

1： ASIC Design Project Leader /数字设计项目经理

工作职责：

1. Responsible for whole chip development and leading digital team to develop digital blocks according to product specifications;

2. Logic design & implementation by Verilog on module level, and chip integration;

3. Design synthesis, CDC checking, timing analysis, DFT and ATPG;

4. Work closely with analog and backend engineer for chip physical design and tape-out;

5. Work closely with application engineer for chip bring-up, debug and solve problem;

6. Good IC verification skills and solid logic and circuit design knowledge, good communication and problem solving skills;

7. Interest of IC project management. Good knowledge of Perl and shell programming would be an added advantage.

职位要求：

1. Bachelor, Master or above in Electronic, Communications, Microelectronics Engineering and Computer Science;

2. At least 8+ years of experience in digital design based on high-level languages (preferable Verilog), with knowledge of ASIC FE design flow, including coding, simulation, verification, synthesis, DFT and STA;

3. Familiar with EDA tools from Synopsis, Cadence or Mentor, like NC-Verilog, VCS, DC and Prime Time;

4. Familiar with video/image process algorithm would be an added advantage;

5. Experience of chip volume production;

6. Familiar with FPGA prototyping development;

7. Familiar with mixed signal or SoC design is better;

8. Good written and oral English communication skills.

职位  2：  Sr. ASIC Design Engineer / 高级数字设计工程师

工作职责：

1.   Logic design & implementation by Verilog on module level, and block integration;

2.   Design synthesis, CDC checking, timing analysis, DFT and ATPG;

3.   Work closely with application engineer for chip bring-up, debug and solve problem;

4.   Good IC verification skills of logic and circuit design, good communication and problem solving skills;

5.   Experience with verification tools such as System Verilog, UVM or System C/Testbuilder, etc.

6.   Good knowledge of Perl and shell programming would be an added advantage.

职位要求：

1.   Bachelor, Master or above in Electronic, Communications, Microelectronics Engineering and

    Computer Science;

2.   At least 5+ years of experience in digital design based on high-level languages (preferable

    Verilog), with knowledge of ASIC FE design flow, including coding, simulation,     

    verification, synthesis, DFT and STA;

3.   Familiar with EDA tools from Synopsis, Cadence or Mentor, like NC-Verilog, VCS, DC and

    Prime Time;

4.   Familiar with video/image process algorithm would be an added advantage;

5.   Familiar with FPGA prototyping development;

6.   Familiar with mixed signal or SoC design is better;

7.   Good written and oral English communication skills.

职位 3：  ASIC Design Engineer / 数字设计工程师

工作职责：

Design and implement digital circuits in advanced CMOS technology;

Develop and improve new and existing circuit solutions;

Present and receive technical feedback at reviews;

Document RTL design and communicate with other designer;

Understand system level architectural design;

Work with team members to resolve technical issues;

职位要求：

Bachelor, Master or above in Electronic, Communications, Microelectronics Engineering, Computer Science or relative major;

At least 3+ years of experience in digital design based on high-level languages (preferable Verilog), with knowledge of ASIC FE design flow, including coding, simulation, verification, synthesis, DFT and STA;

Familiar with front end EDA tools;

Familiar with FPGA prototyping development;

Good written and oral English communication skills.

职位 4：
Sr. Verification Engineer/高级数字验证工程师

工作职责：

1.   Create, developing and maintain verification testbench environment;

2.   Developing test case and regression plans;

3.   Work close with designers and understanding the expected functionality of designs;

4.   Running RTL and gate-level simulations/regression;

5.   Code/functional coverage development, analysis and closure;

6.   Release the documents during the verification flow. Such as verification plan, usage of the verification environment, simulation result of test cases, verification coverage report, etc.

职位要求：

1.   Minimum of 5 years design/verification experience (test plan, test bench, assertions,‎ debugging designs, code coverage etc.);

2.   Knowledge in ASIC/FPGA design process and verification tools/env (UVM/OVM…);

3.   Familiar with design and verification languages (Verilog, System Verilog, SVA etc.);

4.   Familiar with C/C++, Perl/Python and other script/automation skills (tcl, makefile etc);

5.   Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills, English and other foreign languages;

职位 5：  Verification Engineer/数字验证工程师

工作职责：

1.   Understanding the expected functionality of designs;

2.   Designing and developing verification environment;

3.   Running RTL and gate-level simulations/regression;

4.   Code/functional coverage development, analysis and closure;

5.   Release the documents during the verification flow. Such as verification plan, simulation result of test cases, verification coverage report, etc.

职位要求：

1.   Minimum of 3 years design/verification experience (test plan, test bench, assertions,‎ debugging designs, code coverage etc.);

2.   Familiar with design and verification languages (Verilog, System Verilog, SVA etc.);

3.   Scripting and automation skills (tcl, perl, makefile etc) a plus;

4.   Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills, English and other foreign languages;

职位 6：  Leader of Algorithm Development (image / video algorithm)/视频图像算法开发

工作职责：

Manages team of Algorithm Engineers and has strong leadership and motivational skills;

The candidate will be strong in modeling, simulation, evaluation, validation, and hardware implementation of algorithms for display;

Responsible for image / video processing algorithms of the research, design and implementation, as well as the algorithm improvement, optimization for display;

To make Algorithm design requirements, and design Algorithm architecture document, Algorithm primary design documents, Algorithm details design documents;

To co-work and support Software / Hardware / Application engineer to finish system developing.

职位要求：

Master or Doctor of CS / EE / Math or Related Majors with above eight years’ algorithm related experience;

Solid knowledge and experience on C / C++ / matlab and debugging skills;

Strong background in at least one of the following areas:

Image processing, Video pre- or post- processing;

Familiarity with panels (such as LCD, OLED) image processing would be an added advantage;

Knowledge of computer architecture, skill in problem solving and identifying performance bottleneck for algorithm optimization;

Be familiar with ASIC development flow and verification requirement;

Great technical passion, be able to learn new technologies quickly.

职位  7：
Chip Architect/Staff ASIC Design Engineer /芯片架构师/资深数字设计工程师

工作职责：

1. Responsible for architecture definition according to product specifications;

2. Logic design & implementation by Verilog on module level, and chip integration;

3. Design synthesis, timing analysis, DFT and ATPG;

4. Work closely with backend engineer for chip physical design and tape-out;

5. Work closely with application engineer for chip bring-up, debug and solve problem;

6. Good IC verification skills and solid logic and circuit design knowledge, good communication and problem solving skills;

7. Experience with professional verification tools such as System Verilog, VMM/OVM/UVM or System C/Testbuilder, etc. Good knowledge of Perl and shell programming would be an added advantage.

职位要求：

1. Bachelor, Master or above in Electronic, Communications, Microelectronics Engineering and Computer Science;

2. At least 8+ years of experience in digital design based on high-level languages (preferable Verilog), with knowledge of ASIC FE design flow, including coding, simulation, verification, synthesis, DFT and STA;

3. Familiar with EDA tools from Synopsis, Cadence or Mentor, like NC-Verilog, VCS, DC and Prime Time;

4. Familiar with video/image process algorithm would be an added advantage;

5. Experience of chip volume production;

6. Familiar with FPGA prototyping development;

7. Familiar with mixed signal or SoC design is better;

8. Good written and oral English communication skills.