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本帖最后由 dodoee 于 2017-11-15 20:41 编辑
1. The source code documented here and this document are licensed under the GPL v3.0 for non-commercial use. The source is available under a dual source license for commercial use. Please contact asicsolutions.com for more information.
2.GPL-GPU is high performance, small footprint Graphics Processing Unit IP. It is configurable via parameterization to include only the components necessary for a given project. Components are delivered as synthesizable Verilog with constraint guidance and a Verilog testbench. Not all components described within may be available under the GPL license.
3.Key 2D Device Features
The GPLGPU2D includes these features:
PCI Bus Interface.
Optional: AXI, AVALON.
AMBA Memory interface.
Parameterizable 32/ 64/ 128/ 256 bit datapath support.
Integrated Display List Processor with Text mode support.
Transparent BLT and Two operand Bit Blts.
Patterned fills.
Integrated RAMDAC with hardware cursor.
Full Alpha blending.
Lines: Patterned, Poly line, Line with initial error.
Directly supports 8, 16, 32 bits per pixels.
Optional:
Integrated Color Space Converter.
Full color cursor
Configurable memory windows.
4.Key 3D Device Features
The GPLGPU 3D adds these additional features:
3D Lines with setup support
3D Triangles with setup support
Backface culling
Advanced Texture Mapping.
Perspective Correction.
Point Sampling, Bilinear and Trilinear filtering.
Full Level-of-Detail Per-Pixel MIP Mapping.
Full OpenGL Decal, Alpha Blend and Alpha Modulation.
RGB Modulation Lighting Effects.
Separate Texture Mipmapping Minification and Magnification filtering.
Advanced Texture Cache.
Palette textures: 1, 2, and 4 and 8 bit.
Non-Palette textures: 8, 16, and 32 bit.
Direct 8-Bit Palette Index Mode.
Block Diagram
The GPLGPU is partitioned into six functional sections: They are the Host Bus Interface, the Aperture Controller, the Drawing Engine, the CRT Controller, the Memory Controller, and the legacy VGA.
The Host Bus Interface provides an interface to the system bus (PCI, AXI or Avalon). It implements a full PCI slave interface, responding to reads and writes of configuration, memory, and I/O cycles. It also implements a PCI master interface for specific memory writes (See Section 5.6).
The Linear Windows Controller provides address decoding, address translation, color space conversion between the host interface and the local memory system. It also provides a mechanism for caching reads and writes from the host bus to the local buffers. In write mode, up to eight 32 bit words may be written to the host bus cache. The cache continuously monitors the address of each word written to determine if they are in the same page. If the words are not in the same page, or if the cache word count reaches eight, the cache will request the required number of memory writes from the Memory Controller. At this time the cache controller swaps access to its second cache and continues to accept host writes. If another page fault is detected during the secondary cache fill, a system stall will occur. This situation can be avoided by testing the cache and by doing cache line fills. During reads latency will be incurred for initial accesses or any page fault conditions. Software should make an effort to maintain scan line coherency during any access to the local buffers for optimal performance.
The Drawing Engine provides all the required logic to implement BITBLT, LINE, LINE_3D, TRIAN_3D, and HOST XFER commands. The Drawing Engine, when triggered, transfers command and parameter information from the host accessible registers to its own local working registers where it begins its setup phase. When the Drawing Engine is done with its setup, it begins the execution of a specific algorithm for the associated command.
For non-rendering commands, after the setup phase, the Drawing Engine begins requesting memory access from the Memory Controller. For 2D and/or 3D rendering commands, the object is piped through the algorithmic rendering engine which begins requesting memory access from the Memory Controller as soon as the first pixel/texel is generated. Up to 2 rendering commands can be piped through the rendering engine at the same time.
If read data is requested, the memory controller will control the loading of the data into the Drawing Data path and will notify the Drawing Engine that the data is now available. If write data is requested, the data will have been previously setup in the Drawing data path and the Memory controller will control the output of that data to the selected memory buffer.
The Display List Processor (DLP) offloads command generation from the host. When the host is feeding commands, two commands can be written into the GPLGPU before retries will be issued on the bus, impacting system performance. A driver can buffer commands in the off screen memory in a list format. The DLP will automatically parse the list, feeding commands to the GPLGPU without stalling the system. The DLP is double buffered and a list can be appended to while running.
The CRT Controller provides programmable CRT timing signals: horizontal, vertical blanks and syncs. It is also responsible for generating requests to the memory controller for screen refresh cycles. A free running frame counter which generates interrupts to the Host is also provided. This is useful for synchronizing bit map copies. CRT Controller also provides display refresh data for the internal (for SGRAM memory) or external (for WRAM memory) RAMDAC. There is an 8 bit VGA pixel data port when using an external RAMDAC and WRAM memory.
The Memory Controller arbitrates and controls all access to the local memory buffer by the Host Interface, the CRT controller, and the Drawing Engine. This unit provides support for WRAM or SGRAM memory.
For backwards compatibility in a PC system, an optional VGA core can be instantiated. This core is a fully IBM compliant VGA handling all modes. The GPLGPU BIOS contains routines for VESA 3.0 compatibility allowing higher resolution operation.
A Digital DAC is included. For use in an FPGA, an external DVI, DAC, HDMI or DisplayPort Chip will be needed.
gplgpu-master.part01.rar
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gplgpu-master.part02.rar
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补充内容 (2019-8-8 19:36):
gplgpu-master.zip 不用下载，这个没用，传错了，多传了一个 |
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发表于 2017-11-15 13:34:34
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