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10bit,40MS/s,pipeline ADC design using 2.5V 0.25um CMOS.The document includes specification defintion,schematic hierarchy,measure result,and layout.
Hierachy of Schematic
adcchip
adc
bias
clkgen
clkdrvbig
inv_064
inv_slow
nand
nand3i
stage1
adc15
comp1
tgate1
clkdrv
dac15_1
inv_064
nor_064
nor3_064
tgate1
nor_064
sh1
amp2st1
core2st1
tgatex
tgate1
tgatemin
stage2
adc15
comp1
tgatex
clkdrv
dac15_2
inv_064
nor_064
nor3_064
tgate2
nor_064
sh2
amp2st2
core2st2
tgatex
tgate2
tgatemin
stagex
adc15
comp1
tgatex
clkdrv
dac15_x
inv_064
nor_064
nor3_064
tgatex
nor_064
shx
amp2stx
core2stx
tgatex
tgatex
tgatemin
stage9
adc15
comp1
tgatex
clkdrv
nor_064
ddelay
adder
nand
nand3i
xor3i
inv_064
clkdrv
inv_064
invtrs
nand
xor
inv_064
clkinput
pindrv
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E042_PipelineADC.rar
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A very good design example for 10bit pipeline ADC
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