某知名外资企业招聘验证岗位

L1314

SiConTech provides end-to-end chip design and product development services to fabless semiconductor companies and electronic OEMs worldwide for multiple target markets including consumer, storage, wireless, automotive etc. Along with its ecosystem partners, SiConTech is a one-stop-shop place for your complete chip design needs. Founded in 2010, with a strong engineering workforce of over 700 people with extensive IC development skillsets, SiConTech is able to quickly build, scale and deliver ahead of time under challenging schedules. SiConTech is headquartered in India with development and sales office in Bangalore, Hyderabad, Austin, Shanghai, Israel and support locations worldwide.
Job Description:
The verification tasks include block level, chip level verification, test plan creation, scripting, coverage, regression run etc..

Requirements:
The candidate is preferred to be MSEE with minimum of 1+ years, in digital asic/SOC design verification. More experience will be considered as senior engineer or lead.

The candidate should have good understanding on ASIC/SOC design flow and should have:
0. Familiar with one of major verification languages: UVM, C, C++, Systemverilog, Verilog
1. Good knowledge of design verification methodology, such as UVM or OVM and coverage driven verification methodology
2. Many experiences with simulation model creation and the testbench build
3. Strong RTL coding with Verilog and familiar with front-end design flow
4. Background in one of the area below will be a strong plus:
a. Strong C/C++ software development experiences for arm based SoC system
b. Video, display, GPU, DDR, PCIe, USB etc..
5. Be familiar with scripting language, such as Perl, C shell, Makefile.
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