报告如下:
Startpoint : my207/u2_tx/di_buffer_reg_0 (falling edge-triggered flip-flop clocked by I_FCLK)
Endpoint : my207/u2_tx/di_buf_dly_reg_0
(rising edge-triggered flip-flop clocked by TXCLK_DIV11520_OUT)
Path Group: (none)
Path Type: max
Point Incr Path
--------------------------------------------------------------------------------------------
clock_network_delay (ideal) 2.00 2.00
my207/u2_tx/di_buffer_reg_0/CKN (NDRNHSV2) 0.00 2.00 f
my207/u2_tx/di_buffer_reg_0/Q (NDRNHSV2) 0.38 2.38 r
my207/u2_tx/di_buf_dly_reg_0/D (NDRNHSV2) 0.00 2.38 r
data arrival time 2.38
--------------------------------------------------------------------------------------------
(Path is unconstrained)
两个问题:
1.start point是fall edge,end point是rising edge,这样的话dc能正常检查吗
2.这属于跨时钟域的路径,可以问前端这条路径是否真实存在,然后设false_path,现在的问题是为什么会显示Path is unconstrained,是哪里出现问题了吗