hspice2012无法仿真veriloga

justu

我在虚拟机装了lubuntu,然后安装了hspice_vG-2012.06-SP1，破解成功，仿真普通电路没问题，但是如果电路包含了verilog-a，仿真就报错，这是什么原因呢？veriloga编译的模块应该是包含了，不然不会报错无法读取veriloga文件--------------------------------------------------------
|                                                        |
|          Synopsys Unified Verilog-A (pVA v2.0)         |
|                                                        |
|                   Machine Name: felix                  |
| Copyright (c) 2012 Synopsys Inc., All Rights Reserved. |
|                                                        |
--------------------------------------------------------

libepva built by pvamgr synmake_pva_build  on Wed Aug 15 20:00:57 PDT 2012
HSP_HOME:   /eda/synopsys/hspice_vG-2012.06-SP1/hspice
HSP_ARCH:   linux
HSP_GCC :   /eda/synopsys/hspice_vG-2012.06-SP1/hspice/GNU/linux/gcc-4.5.2-static/bin/gcc -m32
HSP_GCC_VER:   4.5.2
Working-Dir: /home/felix/test
Args:        -p hsp -t spi -f apd_iv.pvadir/pvaHDL.lis -o iv.pvadir


Begin of pVA compiling on Sat Jul 29 18:55:50 2017

Parsing './diode.inc'
Parsing include file '/eda/synopsys/hspice_vG-2012.06-SP1/hspice/include/constants.vams'
Parsing include file '/eda/synopsys/hspice_vG-2012.06-SP1/hspice/include/disciplines.vams'

End of pVA compiling on Sat Jul 29 18:55:50 2017


End of build pVA DB on Sat Jul 29 18:55:50 2017

*pvaI* Module (diode): 2 unexpanded port, 0 init, 48 behav, 7 contrib, 39/48 expr(s)
*pvaI*        No DIS, 0 afCount
*pvaI*        0 const-G and 0 const-C, Has switchBranch, 2 bypassOpt.
*pvaI* Module (diode): generated 1 flow node(s) during compilation.
*pvaI* Module (switch1): 3 unexpanded port, 1 init, 7 behav, 1 contrib, 18/48 expr(s)
*pvaI*        Has DIS (AE RD ST), 0 afCount
*pvaI*        0 const-G and 0 const-C, Has switchBranch, 2 bypassOpt.
*pvaI* Module (switch1): generated 0 flow node(s) during compilation.
*pvaI* Module (switch2): 3 unexpanded port, 1 init, 7 behav, 1 contrib, 18/48 expr(s)
*pvaI*        Has DIS (AE RD ST), 0 afCount
*pvaI*        0 const-G and 0 const-C, Has switchBranch, 2 bypassOpt.
*pvaI* Module (switch2): generated 0 flow node(s) during compilation.

End of pVA genC on Sat Jul 29 18:55:50 2017

*pvaI* #### Total 709 line-size(s), 75 expr(s), 9 contr(s), 2 init(s), 62 behav(s), 8 port(s)

Generating iv.pvadir/pvaRTL_linux.so


End of submitting pVA iv.pvadir/pvaRTL.mak on Sat Jul 29 18:55:50 2017

*pvaI* system & gcc return code is 512
**error** Failed to read verilog-A file.
  **error** (iv.ckt:1) difficulty in reading input

justu

没有朋友碰到过啊

henubcl

请问楼主解决了吗？我刚刚遇到同样的问题。