成都Marvell招聘多名 Physical Design and Silicon Validation Engineer

kobefly225

Please check the below JD and send resume to email-box(wujie@marvell.com) if you are interested, thanks!

Job Description of Physical DesignEngineer

Description

• IC design implementation     from RTL to netlist including synthesis, timing constraint composing,     timing eco, design for test
• IC physical     implementation from netlist to GDSII, including floorplanning, power grid     implementation, place and route, clock tree synthesis, timing eco, design     closure, flip-chip design
• IC design verification     including timing analysis, timing signoff, formal verification and low     power verification.
• IC physical verification     including physical verification, crosstalk analysis, power analysis, ESD     analysis, EM analysis.
• Program development in     TCL or Perl to improve productivity.
• You will have the     opportunity to develop next generation IC implementation flow for the most     advance technology.
• As a member of central IC     design team, you will play an important role to assist multiple Marvell’s     business unit with challenge of different physical design jobs.

Qualifications

• BS/MS in ME, EE or CS.
• 1-3 years of hands-on     experience in IC design industry.
• Some experience and     knowledge on process, parameters, synthesis, timing analysis, placement,     routing, CTS, SI, power calculation, custom layout, timing analysis,     DRC/LVS.
• Familiar with Verilog     HDL, Spice;
• Programming-minded,     expert on using Makefile/Tcl/Perl to improve efficiency and streamline     process;
• Can Support complex     physical verification, power signoff, flip-chip and physical     implementation of large scale design with advanced low power feature     independently. Support the flow development of new technology,     methodology.
• Positive, active,     self-motivated team worker, good verbal and written skills in English;
• Real tape-out experience     is a good plus;
• DFT, synthesis, formal     related experiences is a good plus;
• Experiences on Cadence,     Synopsys, Mentor and etc. EDA tools is a good plus.

Job Description of Physical DesignInternship

Description

• Logic synthesis:     including std. cell mapping, timing, power, and area optimization.
• Physical implementation:     including floorplan, power routing, placement, clock tree synthesis,     routing, SI fixing, DRC fixing, timing closure, DFM, Flip Chip Routing.
• Physical verification:     including low power check, timing analysis, timing eco, Xtalk analysis, power     analysis, ESD analysis, EM analysis, DRC check, LVS check, ANT check, ERC     check.
• Tapeout: timing signoff,     power signoff, design tapeout

Qualifications

• MS in ME/EE/CS. Good     GPA required.
• Hands-on experience in coding/circuit design or physical design is     preferred.

·
Self-motivated and team playergood verbal and written skills in English;

·
Working at least four days aweek in the office.

·
To qualify for the job, youshould have some or all of the following technical knowledge and background:

a.
knowledge of Digital Circuit,such as CMOS principle, combinational

   and sequential gate circuit, Layout and ICmanufacture flow.

b.
Knowledge of HDL, such asVerilog, VHDL and reading them easily.

c.
IC design methodologies usingdesign automation EDA tools, ASIC design flow, and deep sub-micron technology.

d.
Familiarization with scriptingprogramming (TCL, Shell or Perl) is preferred.

e.
Known anyone of the EDA tools:

i.
Synopsys: DC, ICC, PT,StartRC…

ii.
Cadence: RC, EDI, INNOVUS,TEMPUS, QRC

iii.
Mentor: Calibre…

Job Description of Silicon ValidationEngineer

Description

As part of Marvellcentral system validationteam, the SV engineer will mainly focus on following areas, but not limited to:

• -Validate different kinds of SoC, including     function validation, performance validation and
• Power consumption     validation. And pre-silicon and post-silicon validation.
       -Develop system level software to cover complex use cases of different     kinds of SoC.
• -Debug complex system     level SoC issues which including software and hardware issues.
       -Cover the temperature, voltage and process validation of the SoC.
• -Support different     product lines as central platform on compliance test.
• -Support different kinds     of SoC bring up and validate the bootrom.

Qualifications

• Master’s degree in electrical engineering, computer engineering or     related technical      fields,
• Good knowledge of C, ARM architecture, embedded system software and     device driver development.
• Knowledge and experience of software and hardware debugging.
• Knowledge of multi-core and multi-thread OS.
• A high-level of self-motivation and a proactive approach to solving     problems.
• Good English communications skills.
• Knowledge of PCIE, SATA, USB, NAND and WIFI is plus.
• Experience of oscilloscope and logic analyzer is plus.