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[招聘] 【Job in consulting】招聘DFT-西安、上海、北京

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发表于 2017-5-23 15:19:24 | 显示全部楼层 |阅读模式

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Designfor Test Engineer (DFT)


Responsibilities:
1.Participate in SoC level DFT architecture definition.
2.Implement DFT strategy for the SoC chips, cooperating with design team
3.Implement basic DFT schemes, including scan, boundary scan, Mem BIST andLogic BIST.
4.Develop the high coverage and cost effective test patterns.
5.Verify all DFT logics and test patterns with simulation and static timinganalysis tool.
6.Support other teams for DFT related problems.
Requirements:
1.Either Bachelor or Master degree, 2+ years related experience required.
2.Basic knowledge of IC design flow, including coding, simulation,verification, synthesis and STA
3.Good understanding of the General DFT methodology such as BIST, SCAN, JTAGand ATPG.
4.Knowledge on and familiar with basic Mentor/ Synopsys DFT flow and tools
5.Proficient in verilog/Vhdl language
6.Be familiar with Shell/TCL/Perl program, or skilled in C program
7.Good English communication skills
8.Self-motivated and good team player


 楼主| 发表于 2017-5-24 10:40:39 | 显示全部楼层
DFT: Design For Test (西安)
ATPG 工程师,要熟悉mentor fastscan 以及 test compress flow. 能够完成DFT设计,验证,以及ATE pattern产生。
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