altran招聘，有兴趣的可以投下简历

chiye87

this is Juanjuan, HR from Altran Technologies, China, we would like to provide you a DFT position, if you are interested in it,please reply to us for further communication. we are looking forward to your kind reply.

Position Title:Design for Test Engineer

Locations:    Beijing /Shanghai/Xi’an

岗位1：Design for Test Engineer (DFT)

职位描述：

Responsibilities:
1.Participate in SoC level DFT architecture definition.
2.Implement DFT strategy for the SoC chips, cooperating with design team
3.Implement basic DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.
4.Develop the high coverage and cost effective test patterns.
5.Verify all DFT logics and test patterns with simulation and static timing analysis tool.
6.Support other teams for DFT related problems.
Requirements:
1.Either Bachelor or Master degree, 2+ years related experience required.
2.Basic knowledge of IC design flow, including coding, simulation, verification, synthesis and STA
3.Good understanding of the General DFT methodology such as BIST, SCAN, JTAG and ATPG.
4.Knowledge on and familiar with basic Mentor/ Synopsys DFT flow and tools
5.Proficient in Verilog/VHDL language
6.Be familiar with Shell/TCL/Perl program, or skilled in C program
7.Good English communication skills
8.Self-motivated and good team player

岗位2：Design and Functional Verification Engineer (DFV)

职位描述：

Responsibilities:
1.According to the design specification, be responsible for the verification plan and verification objective definition.
2.Test-bench development (modeling, assertions, checkers, monitors, score-board, regressions, coverage), test-case development (sequence,VRAD) and integration.
3.Work with Random Verification methodology(VMM, OVM, UVM, eRM)
4.Work as an independent verification engineers to check the design functionality at SOC module level and chip level.
5.Work as interface with Front-End and Back-End engineer to optimize or review the design architecture and implementation.
6.Verilog or VHDL coding according to design specification or external/internal IP integration.
7.Support the post simulation with gate-level verilog or VHDL net list.
Requirements:
1.Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field， 2+ Years of verification working experience.
2.Experience with  Verification language (SPECMAN/E-language, System-Verilog, Vera)
3.Experience with RTL coding and simulators (Modelsim, NC-sim).
4.Basic knowledge of script language (Perl, TCL, C-language and so on)
5.Knowledge about 2G/3G/LTE handset baseband Architecture, ARM, AHB Architecture is a plus.
6.Knowledge about Baseband chip peripheral (USB2.0/USB3.0, SSIC, MIPI) is a plus.
7.Team oriented, love to work in young, international and highly motivated teams.
8.Good command of English

Juanjuan Wei

Altran China

                               
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Room 1708, Tower 2 of Raffles City, No.1191 Changning Road, Changning District
Shanghai, China

Mobile : +(86) 158
2935
6370

juanjuan.wei@altran.com

www.altran.com

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