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请问大神,我一个简单的testbench仿真出不了波形,怎么回事啊?多谢啦!代码如下:
//test bench for sc sdm
`timescale
1ns/1ps
module
sim_sc_sdm ();
reg
clk;
initial
begin
clk
=
1'b0;
#100000 $finish;
end
always
#5 clk=~clk;
initial
begin
$dumpfile("sdm.fsdb");
$dumpvars;
end
endmodule
仿真结果有sdm.fsdb文件,内容如下:
$date
May 18, 2017 05:03:28
$end
$version
TOOL: ncsim 15.10-s010
$end
$timescale
1 ps
$end
$enddefinitions $end
$dumpvars
$end
#100000000
仿真log文件如下:
Loading native compiled code: .................... Done
Design hierarchy summary:
Instances Unique
Modules: 1 1
Registers: 1 1
Always blocks: 1 1
Initial blocks: 2 2
Simulation timescale: 1ps
Writing initial simulation snapshot: worklib.sim_sc_sdm:v
Loading snapshot worklib.sim_sc_sdm:v .................... Done
ncsim> source /opt/cadence/INCISIVE151/tools/inca/files/ncsimrc
ncsim> run
ncsim: *W,DVEXACC: some objects excluded from $dumpvars due to access restrictions, use +access+r on command line for access to all objects.
File: ../test_bench/test.v, line = 18, pos = 8
Scope: sim_sc_sdm
Time: 0 FS + 0
Simulation complete via $finish(1) at time 100 US + 0
../test_bench/test.v:9 #100000 $finish;
ncsim> exit
TOOL: ncverilog 15.10-s010: Exiting on May 18, 2017 at 05:19:25 CST (total: 00:00:00) |
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