每个输出均为循环输出9个数字
代码如下:library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity coefficient9 is
port (clk:in std_logic;
Q7ut std_logic_vector(2 downto 0);
Q15ut std_logic_vector(3 downto 0);
Q16ut std_logic_vector(3 downto 0);
Q17:out std_logic_vector(4 downto 0);
Q31:out std_logic_vector(4 downto 0));
end coefficient9;
architecture Behavioral of coefficient9 is
signal CNT8:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
if CNT8=9 then CNT8<="0000";
else CNT8<=CNT8+1;
end if;
end if;
case CNT8 is
when "0000" => Q7<="111";Q15<="0111";Q16<="0111";Q17<="00111";Q31<="00111";
when "0001" => Q7<="100";Q15<="0100";Q16<="0100";Q17<="00100";Q31<="00100";
when "0010" => Q7<="001";Q15<="1010";Q16<="1100";Q17<="01110";Q31<="01011";
when "0011" => Q7<="101";Q15<="1000";Q16<="0100";Q17<="00000";Q31<="00110";
when "0100" => Q7<="000";Q15<="0100";Q16<="1010";Q17<="00001";Q31<="11110";
when "0101" => Q7<="101";Q15<="1000";Q16<="0100";Q17<="00000";Q31<="00110";
when "0110" => Q7<="001";Q15<="1010";Q16<="1100";Q17<="01110";Q31<="01011";
when "0111" => Q7<="100";Q15<="0100";Q16<="0100";Q17<="00100";Q31<="00100";
when "1000" => Q7<="111";Q15<="0111";Q16<="0111";Q17<="00111";Q31<="00111";
when others => NULL;
end case;
end process;
end Behavioral;