Quartus 16.1 Prime编译问题

xiaoyunvsmm

Quartus 16.1无法编译出计时器？

1. ////
   
2. 
   
3. 
   
4. Project Name: Test01;
   
5. Function: Just test my FPGA board
   
6. Version: 0.1
   
7. Editor: Vincent Li
   
8. Date: 2017-04-03
   
9. 
   
10. clk=50MHz
    
11. 
    
12. ///
    
13. 
    
14. module test01( clk, nRST, LED        );
    
15. 
    
16. input clk,nRST;
    
17. output[3:0] LED;
    
18. 
    
19. parameter T500MS = 25'd24_999_999;
    
20. 
    
21. 
    
22. reg[3:0] rLED;
    
23. reg[24:0] Count;
    
24. 
    
25. always@(posedge clk or negedge nRST)
    
26. if(!nRST)
    
27. Count <= 25'd0;
    
28. else
    
29. Count <= Count + 1'b1;
    
30. 
    
31. 
    
32. always@(posedge clk or negedge nRST)
    
33. if(!nRST)
    
34. rLED <= 4'd1;
    
35. else if(T500MS==25'd24_999_999)
    
36. rLED <= {rLED[2:0],rLED[3]};
    
37. 
    
38. assign LED = rLED;
    
39. 
    
40. 
    
41. endmodule
    

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xiaoyunvsmm

问题已解决， 谢谢大家参观