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楼主 |
发表于 2017-1-18 21:45:42
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Contents
1.
Overview............................................................................................
.................................................. 1
1.1 The Typical UVM Testbench
Architecture................................................................................ 1
1.1.1 UVM Testbench
....................................................................................................
...... 2
1.1.2 UVM Test
....................................................................................................
............... 2
1.1.3 UVM Environment
....................................................................................................
. 2
1.1.4 UVM Scoreboard
....................................................................................................
.... 2
1.1.5 UVM Agent
....................................................................................................
............2
1.1.6 UVM Sequencer
....................................................................................................
..... 3
1.1.7 UVM Sequence
....................................................................................................
....... 3
1.1.8 UVM Driver
....................................................................................................
............ 3
1.1.9 UVM Monitor
....................................................................................................
......... 4
1.2 The UVM Class
Library.............................................................................................
................ 4
2. Transaction-Level Modeling (TLM)
...................................................................................................
7
2.1 Overview
....................................................................................................
................................ 7
2.2 TLM, TLM-1, and TLM-2.0
....................................................................................................
.. 7
2.3 TLM-1 Implementation
....................................................................................................
.......... 8
2.3.1 Basics
....................................................................................................
...................... 8
2.3.2 Encapsulation and Hierarchy
.................................................................................... 12
2.3.3 Analysis Communication
.......................................................................................... 14
2.4 TLM-2.0 Implementation
....................................................................................................
..... 16
2.4.1 Generic Payload
....................................................................................................
.... 16
2.4.2 Core Interfaces and Ports
.......................................................................................... 19
2.4.3 Blocking Transport
...................................................................................................
20
2.4.4 Nonblocking Transport
............................................................................................. 20
2.4.5 Sockets
....................................................................................................
.................. 22
2.4.6 Time
....................................................................................................
...................... 25
2.4.7 Use Models
....................................................................................................
........... 27 |
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