The aempty_n signal might also stay high longer and go low at any moment, even perhaps coincident with the
next read clock edge. If it goes low well before the set-up time of the first synchronize flip-flop, the result is like
scenario (4) above. If it goes low well after the set-up time, the synchronizer will stretch rempty by one more read
clock period.
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发表于 2017-1-7 13:30:55
