关于用verilog语言编写检测开关的问题

Fastearin

如果现在一共有18个拨动开关，用什么样的办法检测被关闭的两个开关是哪？只要求测出最左和最右两端的开关。我自己的思路部分代码如下：

1. input[17:0] rang;
   
2. wire[17:0] rang_1;
   
3. 
   
4. assign rang_1 ={rang[0], rang[1], rang[2],rang[3],rang[4],rang[5],rang[6],rang[7], rang[8],rang[9], rang[10],rang[11],rang[12],rang[13],rang[14],rang[15],rang[16],rang[17]};
   
5. 
   
6. 
   
7. 
   
8. always @(posedge clk or negedge clr_n)
   
9. 
   
10. if(!clr_n)
    
11. 
    
12. left_temp <=5'd0;
    
13. 
    
14. else
    
15. 
    
16. casex(rang)
    
17. 
    
18. 18'b1xxxxxxxxxxxxxxxxx:left_temp <= 5'd1;
    
19. 
    
20. 18'b01xxxxxxxxxxxxxxxx:left_temp <= 5'd2;
    
21. 
    
22. 18'b001xxxxxxxxxxxxxxx:left_temp <= 5'd3;
    
23. 
    
24. 18'b0001xxxxxxxxxxxxxx:left_temp <= 5'd4;
    
25. 
    
26. 18'b00001xxxxxxxxxxxxx:left_temp <= 5'd5;
    
27. 
    
28. 18'b000001xxxxxxxxxxxx:left_temp <= 5'd6;
    
29. 
    
30. 18'b0000001xxxxxxxxxxx:left_temp <= 5'd7;
    
31. 
    
32. 18'b00000001xxxxxxxxxx:left_temp <= 5'd8;
    
33. 
    
34. 18'b000000001xxxxxxxxx:left_temp <= 5'd9;
    
35. 
    
36. 18'b0000000001xxxxxxxx:left_temp <= 5'd10;
    
37. 
    
38. 18'b00000000001xxxxxxx:left_temp <= 5'd11;
    
39. 
    
40. 18'b000000000001xxxxxx:left_temp <= 5'd12;
    
41. 
    
42. 18'b0000000000001xxxxx:left_temp <= 5'd13;
    
43. 
    
44. 18'b00000000000001xxxx:left_temp <= 5'd14;
    
45. 
    
46. 18'b000000000000001xxx:left_temp <= 5'd15;
    
47. 
    
48. 18'b0000000000000001xx:left_temp <= 5'd16;
    
49. 
    
50. 18'b00000000000000001x:left_temp <= 5'd17;
    
51. 
    
52. 18'b000000000000000001:left_temp <= 5'd18;
    
53. 
    
54. default: left_temp <= 5'd0;
    
55. 
    
56. endcase
    
57. 
    
58. 
    
59. 
    
60. always @(posedge clk or negedge clr_n)
    
61. 
    
62. if(!clr_n)
    
63. 
    
64. right_temp <=5'd13;
    
65. 
    
66. else
    
67. 
    
68. casex(rang)
    
69. 
    
70. 18'bxxxxxxxxxxxxxxxxx1:right_temp <= 5'd18;
    
71. 
    
72. 18'bxxxxxxxxxxxxxxxx10:right_temp <= 5'd17;
    
73. 
    
74. 18'bxxxxxxxxxxxxxxx100:right_temp <= 5'd16;
    
75. 
    
76. 18'bxxxxxxxxxxxxxx1000:right_temp <= 5'd15;
    
77. 
    
78. 18'bxxxxxxxxxxxxx10000:right_temp <= 5'd14;
    
79. 
    
80. 18'bxxxxxxxxxxxx100000:right_temp <= 5'd13;
    
81. 
    
82. 18'bxxxxxxxxxxx1000000:right_temp <= 5'd12;
    
83. 
    
84. 18'bxxxxxxxxxx10000000:right_temp <= 5'd11;
    
85. 
    
86. 18'bxxxxxxxxx100000000:right_temp <= 5'd10;
    
87. 
    
88. 18'bxxxxxxxx1000000000:right_temp <= 5'd9;
    
89. 
    
90. 18'bxxxxxxx10000000000:right_temp <= 5'd8;
    
91. 
    
92. 18'bxxxxxx100000000000:right_temp <= 5'd7;
    
93. 
    
94. 18'bxxxxx1000000000000:right_temp <= 5'd6;
    
95. 
    
96. 18'bxxxx10000000000000:right_temp <= 5'd5;
    
97. 
    
98. 18'bxxx100000000000000:right_temp <= 5'd4;
    
99. 
    
100. 18'bxx1000000000000000:right_temp <= 5'd3;
     
101. 
     
102. 18'bx10000000000000000:right_temp <= 5'd2;
     
103. 
     
104. 18'b100000000000000000:right_temp <= 5'd1;
     
105. 
     
106. default: right_temp <= 5'd19;
     
107. 
     
108. endcase
     

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