The design of the top is showing as follows. The software question is logical net 'CLK_OUT' has multiple driver(s). How can I solve the problems ? Thanks a lot.
module top(
input clk,
input rst,
inout[15:0] mcb3_dram_dq,
output[13:0] mcb3_dram_a,
output[2:0] mcb3_dram_ba,
output mcb3_dram_ras_n,
output mcb3_dram_cas_n,
output mcb3_dram_we_n,
output mcb3_dram_odt,
output mcb3_dram_cke,
output mcb3_dram_ck,
output mcb3_dram_ck_n,
inout mcb3_dram_dqs,
inout mcb3_dram_dqs_n,
inout mcb3_dram_udqs,
inout mcb3_dram_udqs_n,
//output mcb3_dram_udm,
output mcb3_dram_dm,
output mcb3_dram_reset_n
);
wire CLK_500M,CLK_100M,CLK_100M_TO;
wire LOCKED;
wire LOCK;
wire tx_SERDESSTROBE;
wire CLK_OUT;
my_pll my_pll_ins
(// Clock in ports
.CLK_IN1(clk), // IN
// Clock out ports
.CLK_OUT1(CLK_500M), // OUT
.CLK_OUT2(CLK_100M), // OUT
.RESET(rst),// IN
.LOCKED(LOCKED)
); // OUT
BUFG BUFG_inst (
.O(CLK_100M_TO), // 1-bit output: Clock buffer output
.I(CLK_100M) // 1-bit input: Clock buffer input
);
BUFPLL #(
.DIVIDE(5)
)
tx_bufpll_inst(
.IOCLK(CLK_OUT),
//OUTPUT
.LOCKED(LOCKED),
//IN
.LOCK(LOCK),
//OUTPUT
.PLLIN(CLK_500M), //IN
.GCLK(CLK_100M_TO), //IN
.SERDESSTROBE(tx_SERDESSTROBE)//OUTPUT
);
my_ipcore # (
.C3_P0_MASK_SIZE(16),
.C3_P0_DATA_PORT_SIZE(128),
.DEBUG_EN(0),
.C3_MEMCLK_PERIOD(3200),
.C3_CALIB_SOFT_IP("TRUE"),
.C3_SIMULATION("FALSE"),
.C3_RST_ACT_LOW(0),
.C3_INPUT_CLK_TYPE("SINGLE_ENDED"),
.C3_MEM_ADDR_ORDER("BANK_ROW_COLUMN"),
.C3_NUM_DQ_PINS(8),
.C3_MEM_ADDR_WIDTH(15),
.C3_MEM_BANKADDR_WIDTH(3)
)
u_my_ipcore (
.c3_sys_clk (CLK_OUT),
.c3_sys_rst_i (rst),
.mcb3_dram_dq (mcb3_dram_dq),
.mcb3_dram_a (mcb3_dram_a),
.mcb3_dram_ba (mcb3_dram_ba),
.mcb3_dram_ras_n (mcb3_dram_ras_n),
.mcb3_dram_cas_n (mcb3_dram_cas_n),
.mcb3_dram_we_n (mcb3_dram_we_n),
.mcb3_dram_cke (mcb3_dram_cke),
.mcb3_dram_ck (mcb3_dram_ck),
.mcb3_dram_ck_n (mcb3_dram_ck_n),
.mcb3_dram_dqs (mcb3_dram_dqs),
.mcb3_dram_dqs_n (mcb3_dram_dqs_n),
.mcb3_dram_dm (mcb3_dram_dm),
.mcb3_dram_reset_n (mcb3_dram_reset_n),
.c3_clk0
(),
.c3_rst0
(),
.c3_calib_done (),
.mcb3_rzq (),
.mcb3_zio (),
.c3_p0_cmd_clk (),
.c3_p0_cmd_en (),
.c3_p0_cmd_instr (),
.c3_p0_cmd_bl (),
.c3_p0_cmd_byte_addr (),
.c3_p0_cmd_empty (),
.c3_p0_cmd_full (),
.c3_p0_wr_clk (),
.c3_p0_wr_en (),
.c3_p0_wr_mask (),
.c3_p0_wr_data (),
.c3_p0_wr_full (),
.c3_p0_wr_empty (),
.c3_p0_wr_count (),
.c3_p0_wr_underrun (),
.c3_p0_wr_error (),
.c3_p0_rd_clk (),
.c3_p0_rd_en (),
.c3_p0_rd_data (),
.c3_p0_rd_full (),
.c3_p0_rd_empty (),
.c3_p0_rd_count (),
.c3_p0_rd_overflow (),
.c3_p0_rd_error ()
);
endmodule |
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发表于 2016-11-13 22:09:19
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